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Original question:

DRA829V: DDRSS Configuration fails with timeout in CCS

DRA829V: Timeout during frequency handshake

Bo Mellberg
Intellectual 611 points

Part Number: DRA829V

Hello experts,

We have a custom board with DRA829V and attached Micron LPDDR4 memory.

The memory is 2GB, compared to the 4GB on the EVM development board. We have
used the Excel tool to try to get the 2GB memory working but to no avail.

Our memory is single rank. The one on the EVM is dual rank. We changed that setting
in the tool but we still get errors during the memory training:

U-Boot SPL 2023.04-g999 (Aug 24 2023 - 07:55:31 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
Timeout during frequency handshake
### ERROR ### Please RESET the board ###

The memory on the EVM is MT53D1024M32D4DT

Our memory is MT53E512M32D1ZW-046 IT:B TR

Any help is really appreciated.

/Bo

  • 0
    Intellectual 611 points

    FYI, the following parameters made the memory run. Don't know if it is correctly set up, but at least we
    now pass the Frequency Handshake.

    /Bo

  • 0 in reply to Bo Mellberg
    TI__Mastermind 43300 points

    Hi Bo,

    So changing the data width from 32 to 16 fixed the issue?

    This seems to indicate that there was an issue with training for the upper 16 bits (channel B), as the part number you provided does appear to have 32x data bits. 

    A few follow-up questions:

    • How consistent is the failure? Do you have the failure count (raw number of failures and number of boot attempts...i.e, "failed 10 out of 12 boot attempts")
    • How many boards does the failure occur on? How many boards have been tested?
    • When the failure occurs, can you please run the attached binary from the R5 core (loads over CCS) and provide the CCS console output?

    tda4vm_lp4_debug.zip

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Intellectual 611 points

    1. The behaviour is consistent, 100%.

    2. All boards.

    3. I won't do this yet. See below.

    I seems our build system is the root cause of this memory issue. We based our custom board build upon the SK-EVM files (dts, dtsi) and it didn't pass the training.

    When I made a test using the common-proc-board.dts as a base, it worked, and I assumed it was because of the parameter changes I had made in the Excel tool. I just tested with the normal parameters, and just changed the rank from 2 to 1 and it works as well for our 2GB memory.

    Now we need to figure out what caused this, and why it doesn't work with the SK files as a base.

  • +1 in reply to Bo Mellberg
    TI__Mastermind 43300 points

    Hi Bo,

    Ok thanks for the update. In terms of DDR configuration, I believe the SK files have different IO settings compared to the EVM. I am not sure what else may be different in the device tree files which would have caused the issue.

    Please let us know if further support is required.

    Thanks,
    Kevin