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Original question:

AM69A: Jacinto high speed Ethernet and interface(AM69A, DRA821U)

AM69: SerDes Configuration Selection

Nicholas Smith1
Prodigy 210 points
Part Number: AM69


In section 12.2.5.1.3.1.1 Table 12-198 of the AM69 TRM (SPRUJ52C), I'm trying to parse through EXACTLY what interfaces can be muxed together in a configuration. Would someone from TI help explain what they mean here?

What is interface alias? Can I select a LANE_FUNC_SEL entry for each column under the SerDes1-4 or is it limited to selecting a single full row?

For example, would someone please walk me through an example selection of interfaces? If there's a tool out there that can walk me through this process, that would be fine as well.

One final question, how many lanes does QSGMII occupy? I'd like to use 2 QSGMII ports for the full 8 outputs, but how would that be configured?

  • +1
    TI__Guru 70290 points

    Hi,

    Nicholas Smith1 said:
    What is interface alias? Can I select a LANE_FUNC_SEL entry for each column under the SerDes1-4 or is it limited to selecting a single full row?

    Interface alias is the functionality of SerDes Lane, Lane will act accordingly as per LANE_FUNC_SEL.
    There is a Lane control register, It will be configured with value of IPx as per functionality (It was taken care in driver)

    As SerDes is a 4 Lanes which means it can support up to 4 Functionalities, But as per clock limitation it supports Max Two functionalities.

    Ex:  
    SerDes4
    Lane0: edp, Lane1: SGMII6, Lane2: HyperLink2, Lane:USB0
    As pointed above we can't use four different functionalities, Max two only possible
    If you want as per above you cane any of 2 Lanes only. 

    Nicholas Smith1 said:
    For example, would someone please walk me through an example selection of interfaces?

    Please refer below are the few of possible configurations from SerDes1 for your understanding:
    1. SGMII-1,2,3,4 Single functionality of SGMII all 4 Lanes are used (It is also possible to configure only 1/2/3 Lanes)
    2. PCIe0x4 - Single  functionality of PCIe all 4 lanes are used (It is also possible to configure only 1/2/3 Lanes)
    3. PCIe + SGMII : All 4 lanes can be used (SGMII- 3,4 PCIe0-Lane2,3 (x2)) (It is also possible to use 2 lanes one each for PCIe0 and SGMII, or 3 also possible 2 for SGMII/PCIe and 1 for PCIe/SGMII), It is Multilink configuration
    4. You can also use QSGMII/XAUI/USXGMII on Port-1 and Port-2 on Lane 2, Lane3 and other Lanes can be used for PCIe/SGMII/XAUI.

    Nicholas Smith1 said:
    If there's a tool out there that can walk me through this process, that would be fine as well.

    There is no tool available or required If your understand above examples and details.

    Nicholas Smith1 said:
    One final question, how many lanes does QSGMII occupy? I'd like to use 2 QSGMII ports for the full 8 outputs, but how would that be configured?

    QSGMII will occupy one SerDes Lane (whatever port we configured as main port, sub ports will not occupy SerDes lanes)
    Ex: Port-1 is configured as main port and 3,4,5 are configured as sub ports then only Port-1 lane of SerDes will be used for QSGMII (as per above SerDes information, it will be SerDes1 Lane2 or SerDes2 Lane2).

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 210 points

    As a final note, if I wanted 2 QSGMII lanes to support a total of 8 1Gbps ports, could I do that on a single SerDes port? I.e. SerDes1 selects QSGMII Lane 3 and 4 for the first two columns and selects PCIe Lane 0 and Lane 1 for the latter 2 columns. Is this possible?

  • 0 in reply to Nicholas Smith1
    TI__Guru 70290 points

    Hi,

    Nicholas Smith1 said:
    As a final note, if I wanted 2 QSGMII lanes to support a total of 8 1Gbps ports, could I do that on a single SerDes port? I.e. SerDes1 selects QSGMII Lane 3 and 4 for the first two columns and selects PCIe Lane 0 and Lane 1 for the latter 2 columns. Is this possible?

    Yes, It is possible in this case you have configure Port-3 and Port-4 are main ports and rest all will be sub ports (here Port-1,2,5, belongs to sub ports of Port-3 and rest 6,7,8 belongs to sub ports of Port-4 i.e. lowest port numbers belongs to part of 1st QSGMII main port).
    Also, the PCI2 in lane-0 and lane-1 were enabled i.e. PCI2 x2 configuration.
    It will be like "QSGMII + PCIe" multilink configuration.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 210 points

    OK, great. Could you please explain what you mean by "sub-ports", though? Here's a quick list of clarifying questions:

    • Are the ports just referring to the ports supported within the CPSW9G subsystem?
    • Is QSGMII Lane 3 referring to Port #3 and Lane 4 to Port #4? I.e. are QSGMII lanes synonymous with ports?
    • And how does the assignment of ports to a particular QSGMII work? Is it a device tree selection or some other configuration?
  • +1 in reply to Nicholas Smith1
    TI__Guru 70290 points

    Hi,

    Nicholas Smith1 said:
    Could you please explain what you mean by "sub-ports", though

    In QSGMII (4 ports being used), only one port is mapped to SerDes lane and which connected to QSGMII PHY.
    The port which is mapped to SerDes lane will usually termed as main port and remaining subordinated ports in QSGMII termed as sub ports.

    Please refer below diagram for better understanding.


    Any of MAC port can be the SerDes lane, In above diagram Port-3 is mapped to SerDes lane and is used for the QSGMII PHY.
    In above Port-3 is QSGMII Port and ports 1,5,7 are QSGMII Sub ports.

    Nicholas Smith1 said:
    Are the ports just referring to the ports supported within the CPSW9G subsystem?

    Yes, port is  nothing but the one of CPSW MAC Port.

    Nicholas Smith1 said:
    Is QSGMII Lane 3 referring to Port #3 and Lane 4 to Port #4? I.e. are QSGMII lanes synonymous with ports?

    Yes, any port can be configured as QSGMII main port so all are mapped to SerDes.

    But, in above image Port-1 and Port-2 were not mentioned with numbers, refer below image. In below Lane-2 is Port-1 and Lane-3 is Port-2 (same in SerDes1 & SerDes2).

    Nicholas Smith1 said:
    And how does the assignment of ports to a particular QSGMII work? Is it a device tree selection or some other configuration?

    In Linux, mapping of port as QSGMII was using device tress selection.
    In case of RTOS application, it is from application Port configuration.
    For more details refer to SDK documentations of RTOS (Ethernet Firmware (Ethfw) related) and Linux (CPSWnG related).

    Best Regards,
    Sudheer