TDA4VH-Q1: OpenVX tivxMemBufferMap/tivxMemBufferUnmap cache consistency problem

li quan

Part Number: TDA4VH-Q1

Hi experts,

I have some questions about the tivxMemBufferMap and tivxMemBufferUnmap functions in the TI OpenVX framework.

1. tivxMemBufferMap performs cache invaild operation, and tivxMemBufferUnmap performs cache write back operation.

2. The versions of VM SDK 7.1 7.3 and 8.1 VM ECO 8.4 VH 8.2 are A72 and do not perform appMemCacheInv and appMemCacheWb operations.
VH SDK 8.5 is that A72 will do both appMemCacheInv and appMemCacheWb during operation.
In VH SDK 8.6, appMemCacheInv does not work, but appMemCacheWb does.

3. Is it because the hardware maintains cache consistency that the VM and ECO platforms do not perform cache operations?
e2e.ti.com/.../tda4vm-why-appmemcachewb-is-blocked-for-a72-in-tivxmembufferunmap tivxMemBufferUnmap#

Does the VH platform need to execute appMemCacheInv and appMemCacheWb?
Does the VH platform need to perform cache operations because the hardware does not support maintaining cache consistency?

Thanks

QuanLi

over 1 year ago

0 Nikhil Dasan over 1 year ago

TI__Guru* 84726 points

Hi QuanLi,

J721E and J721S2 have cache coherency maintained by hardware.

For J784s4, we must do a cache maintenance operation for DSPs that is using MSMC.

Regards,

Nikhil

0 li quan over 1 year ago in reply to Nikhil Dasan

Intellectual 955 points

Hi Nikhil,

Nikhil Dasan said:
For J784s4, we must do a cache maintenance operation for DSPs that is using MSMC.

Do I need to perform cache consistency operations on the A72?

In VH SDK 8.5 is that A72 will do both appMemCacheInv and appMemCacheWb during operation.

But in VH SDK 8.6, appMemCacheInv does not work, appMemCacheWb does for A72，Is there a problem？

Thanks

QuanLi

+1 Nikhil Dasan over 1 year ago in reply to li quan

TI__Guru* 84726 points

Hi,

li quan said:
But in VH SDK 8.6, appMemCacheInv does not work, appMemCacheWb does for A72，Is there a problem？

Thank you for pointing this out. This seems to be a bug in the SDK.

I have raised the bug internally. This will be fixed in the upcoming SDK release.
Placing the jira link here for internal tracking
[TIOVX-1360] Cache Maintaince operation to be removed for A72 - Texas Instruments JIRA

A72 is coherent but C7X is not and thus C7X needs cache maintenance operations enabled.

Regards,

Nikhil

0 li quan over 1 year ago in reply to Nikhil Dasan

Intellectual 955 points

Hi Nikhil,

Nikhil Dasan said:
A72 is coherent but C7X is not and thus C7X needs cache maintenance operations enabled.

The cache flushing function on the unmap operation on the A72 can be deleted, right?

Thanks

QuanLi

0 Nikhil Dasan over 1 year ago in reply to li quan

TI__Guru* 84726 points

Hi QuanLi,

Sorry, there is some discussion happening internally regarding this change.
I shall let you know the outcome once there is a conclusion regarding the same.

I shall try to provide you the conclusion by early next week.

Regards,

Nikhil

0 li quan over 1 year ago in reply to Nikhil Dasan

Intellectual 955 points

Hi Nikhil,

Is there any latest news?

Thanks

QuanLi

0 Nikhil Dasan over 1 year ago in reply to li quan

TI__Guru* 84726 points

Hi,

Sorry for the delay.

The latest on this is that there is no need for a check for the macro for J784s4.

i.e., for both map and unmap function, does not require cache maintainance operation for A72.

Regards,

Nikhil

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TDA4VH-Q1: OpenVX tivxMemBufferMap/tivxMemBufferUnmap cache consistency problem