Other Parts Discussed in Thread: SK-AM62A-LP
Hello,
I have a question regarding the MIPI-Interface in the AM62A.
In order to simplify our Eval-Setup (Routing of the MIPI lines on the adapter PCB) we want to connect our MIPI device to the SK-AM62A-LP Eval-Board by:
a. Swapping the N and P differential lines of data and clock lines
b. Connecting our 2 MIPI data output lines to input lines 1 and 2 on the SoC. Can we connect the data lines like this? or do we have to use line 0 and 1 ?
What I have found out until now and I’m referring to this manual: www.ti.com/.../spruj16b.pdf
1. Chapter “14.9.6.1.32.1 VBUS2APB_VBUSP_APB_CSI2RX_STATIC_CFG” (Page 16321): We can select the number of lanes and the lane mapping here (between CSI Core and MIPI Phy)
2. Chapter “14.9.6.2.9.1 MMR_K3_DPHY_WRAP_LANE Register” (Page 16419): Possibility to swap the differential lines here in the MIPI PHY config registers.
So to me it seems possible to connect our MIPI device like described in a) and b). Somebody can confirm ?
I'm also interested, if this feature is supported by the standard MIPI driver (3.2.2.2. CSI2RX — Processor SDK AM62Ax Documentation) or do we have to modify the driver then?
Thank you for your support:)
Oliver
