PHYTC-3P-KIT-AM64: MCSPI communication TX only mode: Using both data lines for TX to send different data

Hi Guenter,

Apologies in delayed responses. 

Many thanks for your question.

Can you please share your program/project.

That way I can help by going through whats already written.

Regards,

Vaibhav

TX2_mcspi_loopback_am64x-evm_r5fss0-0_nortos_ti-arm-clang.zip

My requirement is to have 1 synchronized clock (5MHz) and 2 data lines with 2 different output streams (appx 400 bits each). 

Hi Guenter,

Thanks for providing the entire project.

I can see a couple of changes in SysConfig and the file "mcspi_loopback.c".

I have noted what your requirement is and I am working on it.

I will update here as soon as I have a progress on this.

Regards,

Vaibhav

Hi Guenter,

I checked internally with the owner of SPI IP.

We cannot send different data on both D0 and D1 since we only have one TX register.

Regards,

Vaibhav

Hi Vaibhav,

Okay. Can we do something with FSI(Fast Serial Interface)? It has one CLK and two data lines (D0 and D1). Do we have any possibility with that? 

Hello Guenter,

I will check FSI internally and let you know my responses within few business days.

Regards,

Vaibhav

Hi Vaibhav,

Thanks for the response.

As I'm also trying to utilise two MCSPIs to make the data transfer. The main idea is to use MCSPI1 as the master and MCSPI0 as a slave so that I can synchronise the two clocks by connecting them externally and then have two transmitting data lines. I've modified the code and sysconfig settings of the mcspi_loopback example but the clock is not visible at the output pins. The modified project is attached below.

mcspi_loopback_nortos_ti-arm-clang.zip

Hello Guenter,

Guenter Egle said:

As I'm also trying to utilise two MCSPIs to make the data transfer. The main idea is to use MCSPI1 as the master and MCSPI0 as a slave so that I can synchronise the two clocks by connecting them externally and then have two transmitting data lines. I've modified the code and sysconfig settings of the mcspi_loopback example but the clock is not visible at the output pins. The modified project is attached below.

I am going through the code and checking the possibility of treating MCSPI0 as the slave. I will also check for the changes in SysConfig you have made.

Expect responses by EOD.

Regards,

Vaibhav

Hi Vaibhav,

Is there any possibility you with MCSPI?

Hello Guenter,

Apologies in delayed responses.

Please allow me one more day to get back to you.

Regards,

Vaibhav

Hello Guenter,

I went through the SysConfig configuration from the project file attached by you.

I have seen that you have configured MCU_SPI1 as the Controller and MCU_SPI0 as the Peripheral.

Yes its possible.

Regards,

Vaibhav

Hi Vaibhav,

Thanks for the response. But actually, I'm not able to see the clock and the data at the output pins(Master and Slave clock are connected physically).

Have I modified the code correctly? It would be a great help if you could check the code.

Thanks in advance!

Hello Guenter,

By physically, do you mean you used jumper wires to connect or is it something else.

Regards,

Vaibhav

Hi Vaibhav,

Yes, I used jumper wires to short the clocks. And at the same junction point, I connected a logic analyzer to see the output.

Hello Guenter,

Thanks for your response.

Meanwhile I go through the code and dig deeper, can you verify which MCSPI configuration you are trying through your application.

Please respond with one of the below.

1. single byte single channel SPI

2. single byte multi channel SPI

3. multi byte single channel SPI

4. multi byte multi channel SPI

Best Regards,

Vaibhav

Hi Vaibhav,

I guess its multi byte multi channel SPI, because we're trying to send 50 bytes of data (diifferent data) through 2 different data lines simultaneously.

Hello Guenter,

Thanks for your response.

Please expect responses within a day.

Regards,

Vaibhav

Hello Guenter,

Your code looks good to me, although I have a little doubt on this part, as your usecase is more like sending data from SPI1 to SPI2. 

Correct me on the above, is your usecase, something like SPI1 to SPI2 and then back to SPI1 ? or simply SPI1 to SPI2.

I am going to try this myself and check.

Can you please tell me are you actually connecting both MCSPIs together with a jumper cable or not.

Best Regards,

Vaibhav

Hi Vaibhav,

Thanks for the response. Actually, I'm not sending the data from master to slave or slave to master. It doesn't sound natural but yes, this is the case. I need to send two data streams parallelly to a peripheral device with a single clock. Data streams are not of exact same length but have nearly 400 bits each. I tried using two Master SPIs but it didn't work for me because two masters have two different Clocks but I need only one. So I thought of using one as Master and the other as a Slave so that the Slave could use the Master's Clock and the same clock could be sent to the peripheral, and then I could send two data streams, one from Master and the other from Slave. I've attached the block diagram pictures to make you understand better.

Thanks again for your efforts

Hi Guenter,

Thanks for the brief explanation along with the block diagram.

I am going through this.

Allow me sometime to comment on this.

Regards,

Vaibhav

Hello Guenter,

Apologies for delayed responses due to TI India Holiday.

Please expect responses within a day or two.

I am checking internally with the validity of the block diagram and then I am going to comment here.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Thanks for the reply. Actually, I doubt if the slave can generate the data to send it to the peripheral. So I tried modifying the block diagram. Here, I'm using one master to generate the clock and data for the slaves, and the two slaves then forward the data to the peripheral. I have attached the block diagram for reference. Could you please do an internal check for this design also? I would be extremely grateful if you could kindly advise whether these two concepts seem feasible and provide me with your guidance regarding any necessary modifications to the project file attached in one of the earlier replies.

Hello Guenter,

Thanks for your response.

I am going to check this block diagram and get back to you in few business days.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hello Guenter,

Guenter Egle said:

.

I checked internally and found out that this block diagram should work.

One thing to keep in mind are; since the data bits are not of the same length for shift register 1 and shift register 2, so they will need to be tolerant of extra bit shifts. 

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Thanks for the reply. But it's not working for me; I can't see any signal related to the slave. Can you please let me know where I did the mistake? I've attached the project file again for your reference.

6557.mcspi_loopback_nortos_ti-arm-clang.zip

Hello Guenter,

Thanks for the code file. I believe this is the same one which you sent earlier.

I see you created two transactions, 1 and 2.

Code looks good to me.

I am seeing if I can reproduce this at my end or check if the signal is coming on the slave.

Please expect follow up questions within a day.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hell Guenter,

Apologies in delayed response.

I am prioritizing your thread at the moment.

Please expect responses by the end of this week.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hello Guenter,

Can you tell me the part number for Board Peripheral device which you have mentioned in the first block diagram. Or maybe point me to which peripheral you are using, so that I can recreate this and check at my end.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Actually, it's a thermal printhead from ROHM Semiconductor. But currently, I'm seeing the data using a logic analyzer LA2016.

Hello Guenter,

Thanks for telling me about the slave here.

Allow me sometime to get back on this.

I am also trying to do SPI between controller and peripheral(sensor) in order to better debug your problem and code.

Can you on the other hand tell me in detail about the connections you have made on SK-AM64?

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hello Guenter,

I am currently having a clear view on the SPI protocol.

I have been able to perform SPI between a TI Processor and a sensor, which gave me deeper insights onto SysConfig configurations of SPI and the code as well.

Basically, we can achieve both half and full duplex communications.

It would be very helpful if you could tell me about the connections you have made for your SPI Block diagram use case.

Post this I can point out the mistake in the connection/code/SysConfig.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Sorry for the delay. Actually, I was not available in the last few days.  I'm actually implementing the idea mainly on the Phytec PHYCORE AM64x board. I also have an AM64x-SK board but am getting the same kind of results. Regarding the connections, there are dedicated pins on the board for the following:

MCU_SPI0_CLK = MCU_GPIO0_11, 

MCU_SPI0_D1 = MCU_GPIO0_4, 

MCU_SPI0_D0 = MCU_GPIO0_10, 

MCU_SPI1_CLK = MCU_GPIO0_7, 

MCU_SPI1_D1 = MCU_GPIO0_9, 

MCU_SPI1_D0 = MCU_GPIO0_8.

Below, I've mentioned the results of four different scenarios:

1. MCU_SPI1 as master alone: MCU_SPI1_CLK and MCU_SPI1_D0 signals are visible in the logic analyzer window

2. MCU_SPI0 as master alone: MCU_SPI0_CLK and MCU_SPI0_D0 signals are visible in the logic analyzer window

3. Both MCU_SPI1 and MCU_SPI0 as masters (No physical connection between the two masters):

Result: CLK and D0 for both the SPIs are visible alternatively (Reference shown in the screenshot attached)

Ch0: MCU_SPI1_CLK, Ch1: MCU_SPI1_D0, Ch8: MCU_SPI0_CLK, Ch9: MCU_SPI0_D0

4. MCU_SPI1 as master and MCU_SPI0 as slave:

Sysconfig settings for MCU_SPI1: 

Mode of operation: Multi Controller

TR Mode: Tx and Rx

Input Select: D1

D0 Tx Enable: Tx Enabled

D1 TX Enable: Tx Disabled

In the Signals block of sysconfig, only D1 is Rx enabled

Sysconfig settings for MCU_SPI0: 

Mode of operation: Single Peripheral

TR Mode: Tx and Rx

Input Select: D0

D0 Tx Enable: Tx Disabled

D1 TX Enable: Tx Enabled

In the Signals block of sysconfig, clock and D0 are Rx enabled

With the above sysconfig settings, these are the results for two cases:

Case1: No physical connections. Result: No signal is visible in the logic analyzer window 

Case2: Clocks are physically connected. Result: No signal is visible in the logic analyzer window 

Again, the aim is to have two different data transfer lines in synchronization with one clock signal.

I hope it explains the situation.

Thanks again for your efforts and patience.

Hi Guenter,

Please expect responses within few business days.

Thanks,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Guenter,

Considering you are using Phytec AM64x Board, so I visited the pinmux tool from Phytec and verified that the connections for MCU_SPI0 and MCU_SPI1 are correct.

But the SysConfig tool is most likely adapted for AM64x. So the base address for each of the D0/D1 and Clock pins might be different, hence I would like you to refer to datasheet/register map and update the base address of the respective peripherals in the file below.

The file is at: MCU_PLUS_SDK_PATH/source/drivers/pinmux/am64x_am243x/pinmux.h

Could you do the same and let me know.

Looking forward to your response.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Thanks for the reply. I've checked the pinmux.h file and all the base addresses are the same as that of the mentioned screenshot by you.

Thanks

Hello Guenter,

I have also cross checked, yes you are correct they are the same.

Please expect responses in few business days, I am checking the code and trying to see what needs modification.

Thanks,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Guenter,

Apologies in delayed responses due to other blocking issues. 

I will respond by tomorrow on this.

Regards,

Vaibhav

Hi Guenter,

Thanks for your patience.

I am going to send out a diagram based of your flow of connections.

Kindly confirm on the same.

Please expect the diagram in a day.

Thanks,

Vaibhav

Hi Vaibhav,

Is there any update on this?

Thanks!

Hi Guenter,

Now the above diagram is basically what you suggested for the first approach.

I had a closer look at the sysconfig file.

I am seeing that MCU_SPI0 has been configured as single peripheral, which make sense. It also has its own CS line enabled.

But, the multi controller configured as MCU_SPI1 has no CS line to offer. In Sysconfig, there is no CS enabled for MCU_SPI1.

I know you have configured it as multi controller for the sake of it operating two supposed to be slaves(MCU_SPI0 and the thermal printhead from ROHM).

Can you please change the MCU_SPI1 mode of operation to single controller and enable the CS line.

Looking forward to your response.

Regards,

Vaibhav