SK-TDA4VM: The last 1pixel of the DSS (HDMI) output image is a black bar

Hi Qibin Su

Is the size specified in the overlay manager matching with the input frame size? If there is any slight different in the size, this color can then come from the overlay manager. 

Regards,

Brijesh

Hi Brijesh,

Our Display Initialization and Display Pipeline are configured according to your document:8.14. Changing Display Resolution in Vision Apps — Processor SDK RTOS J721E, and the resolution of the two configurations is the same. I don't quite understand whether overlay manager you refer to these two configurations.

Best Regards

Hi Qibin su,

I meant to ask, if the display output resolution is same input resolution? Lets says, if the display output resolution is 1920x1080 and input from the video pipeline is configured for lower resolution, like 1920x1079, then there is a possibility that there is black line at the end of the image. 

I see you are using BT601 output format from the above screen shot. Is there a possibility that vertical timing parameters are not configured correctly? or may be on the receiver side the polarity of hs or vs signals are not matching? 

Regards,

Brijesh

Hi Brijesh,

We found that the entire screen is shifted forward by 1 line and the last line is filled with 80 10.

Could you give some suggestions? If our BT601 timing setting is OK?

BR

Hi,

No the timing looks to be correct. Can you please dump TIMING_H and TIMING_V registers for both the VP output and share them? 

Also is there a possibility that the issue is coming due to incorrect polarity ? Have you tried changing polarity of vsync? 

Regards,

Brijesh

1. dump TIMING_H and TIMING_V registers 

1.1 DSS0_VP_TIMING_H：
DSS0_VP2 0x04AA0054h:Value at addr 0x4aa0054 = 0x000000d3
DSS0_VP3 0x04AC0054h:Value at addr 0x4ac0054 = 0x09f0c73b

1.2 DSS0_VP_TIMING_V：
DSS0_VP2 0x04AA0058h:Value at addr 0x4aa0058 = 0x00d00f00
DSS0_VP3 0x04AC0058h:Value at addr 0x4ac0058 = 0x00a00f04

2.  Have you tried changing polarity of vsync?

We try to change serializer's VS/HS/DE polarity, but no effect.

Hi,

when usecase is running, can you try changing value at 0x4aa0058 to 0x00E00f00? Lets see if this makes any difference. 

Regards,

Brijesh

can you try changing value at 0x4aa0058 to 0x00E00f00?

----> Please refer to 

ok it seems to go out of sync from the VP, which is outputting data. 

I guess we need to change timing on both the outputs. 

Lets say if we increase vertical front porch and reduce vertical back porch, does it help? 

Can you try with below timing?

Regards,

Brijesh

Hi Brijesh,

We try the new timing,but no effect. 

Thanks

Hi henry wu,

Are you sure that there is no cropping and/or timing issue on the receiving end? Is there a possibility that receiver is wrongly detect vsync and skipping one active video line? 

Or the other way is, we can try increasing backporch and see if it helps?

Regards,

Brijesh

Hi Brijesh,

We measured the waveform，it shows the VBP and VFP are not correct. Trying to change VBP and VFP setting like below:

the waveform is OK but Date we caught ,The last line is still a black line.

the wrong waveform like below:

Hi Henry Wu,

ok, i am trying to match embedded sync program as per above, so can you please try with below settings?

Regards,

Brijesh

Hi Brijesh,

We tried this settings, but no effect. this issue also happen.

BR

Hi Brijesh,

Could you help check why the  VFP and VBP timing are not mached with the code setting?

BR

Hi henry wu,

Sorry, did not get your question. Are you checking in the register to confirm the settings? For which output do you see VFP and VBP mismatching? 

Regards,

Brijesh

Hi Brijesh,

We measured the waveform showed before. We set VP2 and VP3 according the below table:

The wavefore we got by measured VS in DPI is not matched the VFP 15 and VBP 10 timing. We get VFP is 16 and VBP is 9 clock in waveform.

You could refer to waveform we provided before

BR

Hello Henry Wu,

Can you please readback  VP_TIMING_H and  VP_TIMING_V registers for both the VPs and share them?

According to above table, they should have been configured 15 and 10 lines.. 

Regards,

Brijesh

Hi Brijesh,

Pls refer to below:

1.1 DSS0_VP_TIMING_H：
DSS0_VP2 0x04AA0054h:Value at addr 0x4aa0054 = 0x000000d3
DSS0_VP3 0x04AC0054h:Value at addr 0x4ac0054 = 0x09f0c73b

1.2 DSS0_VP_TIMING_V：
DSS0_VP2 0x04AA0058h:Value at addr 0x4aa0058 = 0x00d00f00
DSS0_VP3 0x04AC0058h:Value at addr 0x4ac0058 = 0x00a00f04

BR

Hi Henry, 

But as per this register, VFP and VBP are setup correctly ie 0x00a00f04. VFP is set to 15 and VBP is set to 10.  

Can you try one more experiment? Can you try changing value at 0x4aa0058 to 0x00e00f00 or 0x00F00f00 and see if there is any difference?

Regards,

Brijesh

Hi Brijesh,

We tried it,the case like before. Pls refer to the video provided before, the graphic is flushed from up to down with black bar(VFP + VBP lines)

BR

Hi Brijesh,

But we tried to change 0x4aa0058  to 0x00e00e00 and it work, black line is gone. So could you help check the possible reason, if any side effects if we just only change VFP and VBP to 0xe?

BR

Hi henry,

No side effect of this change, somehow the blanking line is getting included in the active area, so i just increased blanking area by 1 line, 

Regards,

Brijesh

Hi Brijesh,

The VP timing setting we refer to /cfs-file/__key/communityserver-discussions-components-files/791/BT601_2D00_TimingCalc.zip.

So in our case, it seems a common issue, if the TimingCalc tool need updated?

BR

Hi Henry,

No, this calculator is used by multiple customers and have not seen this issue. 

In your case, this seems to be special case. Maybe in your case, instead of reducing VBP by 2 in the excel sheet, can you reduce both VFP and VBP by 1? 

Regards,

Brijesh

Hi Brijesh,

Below is our final settings, could you help check if OK and could be applied?

Change the VP2's VBP and VFP to 14.

BR

Hi Henry,

Yes, it looks fine to me. 

Regards,

Brijesh