AM623: AUDIO_EXT_REFCLK1 input

li weiyu

Expert 1090 points

Part Number: AM623
Other Parts Discussed in Thread: TLV320AIC3101, TAS2780

Hi, TI expert!

I have a development environment for am6234, with our own evaluation board.

The evaluation board has a tlv320aic3101 audio codec chip.

The software SDK version is PROCESSOR-SDK-LINUX-RT-AM62X-08.06.00.42.

We attempted to use the mcasp of am6234 as the master device and the tlv320aic3101 codec chip as the slave device in I2S mode to record and playback a sound.

On the hardware side, we will connect a 12.288MHz crystal oscillator to the AUDIO_EXT_REFCLK1 pin, which will serve as an input and provide a clock signal of 12.288MHz to the AHCLKX of mcasp on am62x, as followings:

Now, for the software modifications, how should we modify the device tree and source code? Is there a detailed method for making these modifications?

Regards,

over 2 years ago

0 Suren Porwar over 2 years ago

TI__Mastermind 28735 points

Hi Li,

Whatever DTS changes you have done in the below thread is correct for making mcasp as master:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1271393/am623-mcasp-i2s-master

I am waiting for inputs from our SW team on why you are not able to see the clocks correctly. Please give me a day or two to respond back. Apologies for the delay.

Best Regards,

Suren

0 li weiyu over 2 years ago in reply to Suren Porwar

Expert 1090 points

Hi Suren,

The week is almost over, and we are quite anxious over here. Has there been any reply from the software team?

Best Regards,

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

Hi Suren,

Is there any new progress on this issue?

Best Regards,

0 Suren Porwar over 1 year ago in reply to li weiyu

TI__Mastermind 28735 points

Hi Li,

Can you verify your setup on SDK 9.0 release and let us know if you still see the issue?

Here are few recommendations that you could try on your 8.6 setup:

manually request 25Mhz from k3conf,

# k3conf set clock 157 18 25000000

# k3conf dump clock 157

See if this solves or fails on your end and let us know.

But the recommendation is to use McASP as slave and codec as master. McASP as master does not accurately hit the bitrate required for any of the usual sample rates (44.1Khz/48Khz and their factors), and the you have to do the painstaking process of figuring out the right auxclk (96Mhz or 100Mhz) to sample-rate ratio that gets it close, to update in the DT node. Because of this, is what you are seeing bitclk being sped up on your setup.

Best Regards,

Suren

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

Hi Suren,

The output after executing the command is shown in the following log:


data-mode="text">root@am62xx:~# k3conf set clock 157 18 25000000 --------------------------------------------------------------| | --------------------------------------------------------------| (version v0.1-88-g982f5c2 built Mon Jun 26 06:16:37 UTC 2023)         | | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') | --------------------------------------------------------------| neric_fprint(): WARNING: "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLKCLK_STATE_READY" size (115) > TABLE_MAX_ELT_LEN (100)! ---------------------------------------------------------------------------------------------------------------------------------------------------| | Clock ID | Clock Name                                                                                           | Status              | Clock Frequency | ---------------------------------------------------------------------------------------------------------------------------------------------------| 0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                                      | CLK_STATE_READY     | 25000000        | 1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                           | CLK_STATE_READY     | 96000000        | 8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                            | CLK_STATE_READY     | 25000000        | 9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                                     | CLK_STATE_READY     | 0               | 10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                                      | CLK_STATE_READY     | 25000000        | 11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                           | CLK_STATE_READY     | 96000000        | 18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                            | CLK_STATE_READY     | 25000000        | 19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                                     | CLK_STATE_READY     | 0               | 20    | DEV_BOARD0_CLKOUT0_IN                                                                                | CLK_STATE_READY     | 50000000        | 21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5                                      | CLK_STATE_READY     | 50000000        | 22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10                                     | CLK_STATE_READY     | 25000000        | 23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                                                | CLK_STATE_READY     | 0               | 24    | DEV_BOARD0_DDR0_CK0_IN                                                                               | CLK_STATE_READY     | 250000000       | 25    | DEV_BOARD0_DDR0_CK0_N_IN                                                                             | CLK_STATE_READY     | 0               | 27    | DEV_BOARD0_DDR0_CK0_OUT                                                                              | CLK_STATE_READY     | 0               | 33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                                           | CLK_STATE_READY     | 0               | 34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                                            | CLK_STATE_READY     | 0               | 35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                                           | CLK_STATE_READY     | 0               | 36    | DEV_BOARD0_GPMC0_CLK_IN                                                                              | CLK_STATE_READY     | 0               | 37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                                         | CLK_STATE_READY     | 133333333       | 38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                                | CLK_STATE_READY     | 133333333       | 39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK                               | CLK_STATE_READY     | 100000000       | 40    | DEV_BOARD0_I2C0_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 41    | DEV_BOARD0_I2C0_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 42    | DEV_BOARD0_I2C1_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 43    | DEV_BOARD0_I2C1_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 44    | DEV_BOARD0_I2C2_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 45    | DEV_BOARD0_I2C2_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 46    | DEV_BOARD0_I2C3_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 47    | DEV_BOARD0_I2C3_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               | 50    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               | 51    | DEV_BOARD0_MCASP0_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               | 52    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               | 53    | DEV_BOARD0_MCASP0_AFSR_IN                                                                            | CLK_STATE_READY     | 0               | 54    | DEV_BOARD0_MCASP0_AFSX_IN                                                                            | CLK_STATE_READY     | 0               | 55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               | 56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               | 57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               | 58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               | 59    | DEV_BOARD0_MCASP1_AFSR_IN                                                                            | CLK_STATE_READY     | 0               | 60    | DEV_BOARD0_MCASP1_AFSX_IN                                                                            | CLK_STATE_READY     | 0               | 61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               | 62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               | 63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               | 64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               | 65    | DEV_BOARD0_MCASP2_AFSR_IN                                                                            | CLK_STATE_READY     | 0               | 66    | DEV_BOARD0_MCASP2_AFSX_IN                                                                            | CLK_STATE_READY     | 0               | 67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                                       | CLK_STATE_READY     | 0               | 68    | DEV_BOARD0_MCU_I2C0_SCL_IN                                                                           | CLK_STATE_READY     | 0               | 69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                                          | CLK_STATE_READY     | 0               | 70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                                            | CLK_STATE_READY     | 12500000        | 71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                                                 | CLK_STATE_READY     | 12500000        | 72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                             | CLK_STATE_READY     | 25000000        | 73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                                           | CLK_STATE_READY     | 0               | 75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                                           | CLK_STATE_READY     | 0               | 77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                                         | CLK_STATE_READY     | 100000000       | 78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                                          | CLK_STATE_READY     | 0               | 79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                                          | CLK_STATE_READY     | 0               | 80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                                          | CLK_STATE_READY     | 0               | 81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                                          | CLK_STATE_READY     | 0               | 82    | DEV_BOARD0_MDIO0_MDC_IN                                                                              | CLK_STATE_READY     | 0               | 83    | DEV_BOARD0_MMC0_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               | 84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               | 86    | DEV_BOARD0_MMC0_CLK_OUT                                                                              | CLK_STATE_READY     | 0               | 87    | DEV_BOARD0_MMC1_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               | 88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               | 89    | DEV_BOARD0_MMC1_CLK_IN                                                                               | CLK_STATE_READY     | 0               | 90    | DEV_BOARD0_MMC1_CLK_OUT                                                                              | CLK_STATE_READY     | 0               | 91    | DEV_BOARD0_MMC2_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               | 92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               | 93    | DEV_BOARD0_MMC2_CLK_IN                                                                               | CLK_STATE_READY     | 0               | 94    | DEV_BOARD0_MMC2_CLK_OUT                                                                              | CLK_STATE_READY     | 0               | 95    | DEV_BOARD0_OBSCLK0_IN                                                                                | CLK_STATE_READY     | 500000000       | 96    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 500000000       | 97    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 192000000       | 98    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 333333333       | 99    | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT                                                  | CLK_STATE_READY     | 12500000        | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8                             | CLK_STATE_READY     | 30637           | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0                                  | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                                 | CLK_STATE_READY     | 25000000        | | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK0_MUX_SEL_DIV_CLKOUT                                         | CLK_STATE_READY     | 32552           | | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK                                        | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 350000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 170000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                            | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_CLK_32K_RC_SEL_OUT0                                                     | CLK_STATE_READY     | 32768           | | DEV_BOARD0_OSPI0_DQS_OUT                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_OSPI0_LBCLKO_IN                                                                           | CLK_STATE_READY     | 0               | | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_RXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_TXC_IN                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_TXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII2_RXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII2_TXC_IN                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII2_TXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RMII                                                    | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI1_CLK_IN                                                                               | CLK_STATE_READY     | 0 | DEV_BOARD0_SPI2_CLK_IN                                                                               | CLK_STATE_READY     | 0               | | DEV_BOARD0_SYSCLKOUT0_IN                                                                             | CLK_STATE_READY     | 125000000       | | DEV_BOARD0_TCK_OUT                                                                                   | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO0_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO1_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO2_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO3_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO4_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO5_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO6_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO7_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TRC_CLK_IN                                                                                | CLK_STATE_READY     | 0               | | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                                       | CLK_STATE_READY     | 0               | | DEV_BOARD0_VOUT0_PCLK_IN                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_WKUP_CLKOUT0_IN                                                                           | CLK_STATE_READY     | 32768           | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                            | CLK_STATE_READY     | 25000000        | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_LFOSC0_CLKOUT                                            | CLK_STATE_READY     | 32768           | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                                  | CLK_STATE_READY     | 200000000       | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                                  | CLK_STATE_READY     | 192000000       | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK                                 | CLK_STATE_READY     | 50000000        | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_CLK_32K_RC_SEL_OUT0                                                | CLK_STATE_READY     | 32768           | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT                                             | CLK_STATE_READY     | 12500000        | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0                                       | CLK_STATE_READY     | 25000000        | ---------------------------------------------------------------------------------------------------------------------------------------------------| --------------------------------------------------------------| | --------------------------------------------------------------| (version v0.1-88-g982f5c2 built Mon Jun 26 06:16:37 UTC 2023)         | | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') | --------------------------------------------------------------| neric_fprint(): WARNING: "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLKCLK_STATE_READY" size (115) > TABLE_MAX_ELT_LEN (100)! ---------------------------------------------------------------------------------------------------------------------------------------------------| | Clock ID | Clock Name                                                                                           | Status              | Clock Frequency | ---------------------------------------------------------------------------------------------------------------------------------------------------| 0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                                      | CLK_STATE_READY     | 25000000        | 1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                           | CLK_STATE_READY     | 96000000        | 8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                            | CLK_STATE_READY     | 25000000        | 9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                                     | CLK_STATE_READY     | 0               | 10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                                      | CLK_STATE_READY     | 25000000        | 11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               | 14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               | 17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                           | CLK_STATE_READY     | 96000000        | 18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                            | CLK_STATE_READY     | 25000000        | 19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                                     | CLK_STATE_READY     | 0               | 20    | DEV_BOARD0_CLKOUT0_IN                                                                                | CLK_STATE_READY     | 50000000        | 21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5                                      | CLK_STATE_READY     | 50000000        | 22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10                                     | CLK_STATE_READY     | 25000000        | 23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                                                | CLK_STATE_READY     | 0               | 24    | DEV_BOARD0_DDR0_CK0_IN                                                                               | CLK_STATE_READY     | 250000000       | 25    | DEV_BOARD0_DDR0_CK0_N_IN                                                                             | CLK_STATE_READY     | 0               | 27    | DEV_BOARD0_DDR0_CK0_OUT                                                                              | CLK_STATE_READY     | 0               | 33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                                           | CLK_STATE_READY     | 0               | 34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                                            | CLK_STATE_READY     | 0               | 35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                                           | CLK_STATE_READY     | 0               | 36    | DEV_BOARD0_GPMC0_CLK_IN                                                                              | CLK_STATE_READY     | 0               | 37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                                         | CLK_STATE_READY     | 133333333       | 38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                                | CLK_STATE_READY     | 133333333       | 39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK                               | CLK_STATE_READY     | 100000000       | 40    | DEV_BOARD0_I2C0_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 41    | DEV_BOARD0_I2C0_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 42    | DEV_BOARD0_I2C1_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 43    | DEV_BOARD0_I2C1_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 44    | DEV_BOARD0_I2C2_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 45    | DEV_BOARD0_I2C2_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 46    | DEV_BOARD0_I2C3_SCL_IN                                                                               | CLK_STATE_READY     | 0               | 47    | DEV_BOARD0_I2C3_SCL_OUT                                                                              | CLK_STATE_READY     | 0               | 49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               | | CLK_STATE_READY     | 0               | 53    | DEV_BOARD0_MCASP0_AFSR_IN                                                                            | CLK_STA         | 54    | DEV_BOARD0_MCASP0_AFSX_IN                                                                            | CLK_STATE_READY     | 0               | 55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               | 56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               | 57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               | 58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               | 59    | DEV_BOARD0_MCASP1_AFSR_IN                                                                            | CLK_STATE_READY     | 0               | 60    | DEV_BOARD0_MCASP1_AFSX_IN                                                                            | CLK_STATE_READY     | 0               | 61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               | 62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               | 63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               | 64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               | 65    | DEV_BOARD0_MCASP2_AFSR_IN                                                                            | CLK_STATE_READY     | 0               | 66    | DEV_BOARD0_MCASP2_AFSX_IN                                                                            | CLK_STATE_READY     | 0               | 67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                                       | CLK_STATE_READY     | 0               | 68    | DEV_BOARD0_MCU_I2C0_SCL_IN                                                                           | CLK_STATE_READY     | 0               | 69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                                          | CLK_STATE_READY     | 0               | 70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                                            | CLK_STATE_READY     | 12500000        | 71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                                                 | CLK_STATE_READY     | 12500000        | 72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                             | CLK_STATE_READY     | 25000000        | 73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                                           | CLK_STATE_READY     | 0               | 75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                                           | CLK_STATE_READY     | 0               | 77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                                         | CLK_STATE_READY     | 100000000       | 78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                                          | CLK_STATE_READY     | 0               | 79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                                          | CLK_STATE_READY     | 0               | 80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                                          | CLK_STATE_READY     | 0               | 81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                                          | CLK_STATE_READY     | 0               | 82    | DEV_BOARD0_MDIO0_MDC_IN                                                                              | CLK_STATE_READY     | 0               | 83    | DEV_BOARD0_MMC0_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               | 84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               | 86    | DEV_BOARD0_MMC0_CLK_OUT                                                                              | CLK_STATE_READY     | 0               | 87    | DEV_BOARD0_MMC1_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               | 88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               | 89    | DEV_BOARD0_MMC1_CLK_IN                                                                               | CLK_STATE_READY     | 0               | 90    | DEV_BOARD0_MMC1_CLK_OUT                                                                              | CLK_STATE_READY     | 0               | 91    | DEV_BOARD0_MMC2_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               | 92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               | 93    | DEV_BOARD0_MMC2_CLK_IN                                                                               | CLK_STATE_READY     | 0               | 94    | DEV_BOARD0_MMC2_CLK_OUT                                                                              | CLK_STATE_READY     | 0               | 95    | DEV_BOARD0_OBSCLK0_IN                                                                                | CLK_STATE_READY     | 500000000       | 96    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 500000000       | 97    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 192000000       | 98    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 333333333       | 99    | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT                                                  | CLK_STATE_READY     | 12500000        | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                                 | CLK_STATE_READY     | 25000000        | | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK0_MUX_SEL_DIV_CLKOUT                                     STATE_READY     | 32552           | | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK                                        | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 400000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 350000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 170000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                            | CLK_STATE_READY     | 500000000       | | DEV_BOARD0_OBSCLK0_IN_PARENT_CLK_32K_RC_SEL_OUT0                                                     | CLK_STATE_READY     | 32768           | | DEV_BOARD0_OSPI0_DQS_OUT                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_OSPI0_LBCLKO_IN                                                                           | CLK_STATE_READY     | 0               | | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                                          | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_RXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_TXC_IN                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII1_TXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII2_RXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII2_TXC_IN                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_RGMII2_TXC_OUT                                                                            | CLK_STATE_READY     | 0               | | DEV_BOARD0_RMII1_REF_CLK_OUT                                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_RMII2_REF_CLK_OUT                                                                         | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI0_CLK_IN                                                                               | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI1_CLK_IN                                                                               | CLK_STATE_READY     | 0               | | DEV_BOARD0_SPI2_CLK_IN                                                                               | CLK_STATE_READY     | 0               | | DEV_BOARD0_SYSCLKOUT0_IN                                                                             | CLK_STATE_READY     | 125000000       | | DEV_BOARD0_TCK_OUT                                                                                   | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO0_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO1_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO2_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO3_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO4_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO5_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO6_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TIMER_IO7_IN                                                                              | CLK_STATE_READY     | 0               | | DEV_BOARD0_TRC_CLK_IN                                                                                | CLK_STATE_READY     | 0               | | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                                       | CLK_STATE_READY     | 0               | | DEV_BOARD0_VOUT0_PCLK_IN                                                                             | CLK_STATE_READY     | 0               | | DEV_BOARD0_WKUP_CLKOUT0_IN                                                                           | CLK_STATE_READY     | 32768           | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                            | CLK_STATE_READY     | 25000000        | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_LFOSC0_CLKOUT                                            | CLK_STATE_READY     | 32768           | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                                  | CLK_STATE_READY     | 200000000       | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                                  | CLK_STATE_READY     | 192000000       | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK                                 | CLK_STATE_READY     | 50000000        | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_CLK_32K_RC_SEL_OUT0                                                | CLK_STATE_READY     | 32768           | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT                                             | CLK_STATE_READY     | 12500000        | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0                                       | CLK_STATE_READY     | 25000000        | ---------------------------------------------------------------------------------------------------------------------------------------------------|

We also noticed that it is difficult to obtain a commonly used frame clock, such as 44.1Khz/48Khz, through auxclk.
So our idea is to externally connect a 12.288Mhz crystal oscillator to the AUDIO_EXT_REFCLK1 pin of am6234, and use the crystal oscillator and mcasp to generate the required frame clock (ACLKX), just as described at the beginning of this post.
Can this concept be realized? If so, how should the code and device tree be modified?

Best Regards,
Li

0 Suren Porwar over 1 year ago in reply to li weiyu

TI__Mastermind 28735 points

Hi Li,

When you set the frequency to 25MHz using k3conf, are you able to play the audio? Also are all the clocks correctly displayed on the oscilloscope?

Best Regards,

Suren

0 Suren Porwar over 1 year ago in reply to Suren Porwar

TI__Mastermind 28735 points

Also, if you are using an external osciallator, why would you not drive the clocks from the codec? Meaning, make codec as master and McASP as slave.. (Which is what our current AM62x with AIC3106 codec confifuration is), where you would not have to modify the DTS entries? Is there a specific reason, you want McASP to be master?

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

Hi Suren,

Our client is using a codec chip with model number tas2780, which is unable to generate clock and can only function as an audio slave device, hence requiring mcasp to be set as the master device.

Currently, we are aiming to debug with the AIC3106 to ensure that mcasp can output normal bit clock and frame clock when configured as the master device and AIC3106 as the slave device.

Best Regards,

0 Suren Porwar over 1 year ago in reply to li weiyu

TI__Mastermind 28735 points

Hi Li,

Do let me know your observations when you make McASP is configured as master device and AIC3106 as slave.

Best Regards,

Suren

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

Hi Suren,

When MCASP is configured as a master device and AIC3106 is configured as a slave device, we can record and play sound normally.

Best Regards,

0 Suren Porwar over 1 year ago in reply to li weiyu

TI__Mastermind 28735 points

I am glad that it works fine.

Could you share what changes you had to do in order to make it work?

Best Regards,

Suren

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

I'm sorry，When MCASP is configured as a master device and AIC3106 is configured as a slave device, it Still not working，The observed phenomenon is described in the following post:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1271393/am623-mcasp-i2s-master

Do you have a solution to the question raised by this post?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1272002/am623-audio_ext_refclk1-input/4844633#4844633

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

Do your audio experts have any new feedback? Almost a month has passed since the posting time, but this problem（MCASP configured as a master device and AIC3106 configured as a slave device）is still no solved, and our project is in a hurry.

0 li weiyu over 1 year ago in reply to Suren Porwar

Expert 1090 points

any updates today?

0 Suren Porwar over 1 year ago in reply to li weiyu

TI__Mastermind 28735 points

Hi Li,

Sincere apologies for the delay.

This Patch series was validated on AM62x. Can you verify the same on your end and see if you haven't missed anything?

https://lore.kernel.org/all/20230807202159.13095-1-francesco@dolcini.it/

check k3conf to see the clock rate being updated, and use devmem2 to dump the mux register showing that ext_ref_clk is being routed out.

We can setup a call to explain the clocking mux regarding the AUDIO_EXT_REFCLK routing, once you have verified the patch series above.

Best Regards,

Suren

0 Suren Porwar over 1 year ago in reply to Suren Porwar

TI__Mastermind 28735 points

Hi Li,

If you are providing 12.288MHz to the AHCLKX of mcasp, Can you please share the register dump of McASP and also what BCLK and Frame sync are you seeing on the oscilloscope?

You don't need to change anything as you are using AUDIO_EXT_REFCLK1 pin of am6234 as Input, the only thing you need to see if BCLK and FSX are properly generated in order to drive those clocks as Master.

The syscon node changes are required only when you want to use AUDIO_EXT_REFCLK as output for external peripherals.

As I said earlier, we can setup a call to discuss if things are not clear.

Hope this helps.

Best Regards,

Suren

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AM623: AUDIO_EXT_REFCLK1 input