TMS320C6678: DDR3 bit error involving clock generator and AC coupling (continued)

Bump.

Hi Robert,

Thanks for providing register dumps. Can you also collect values from the PHY registers? (DDR3_CONFIG_0 through DDR3_CONFIG_60)

On the failing board, you show that STATUS = 0x40000064.

According to https://www.ti.com/lit/pdf/sprugv8 , this indicates that RDLVL gate and RD data eye training timed out.

There is an advisory for RD data eye training (see Advisory 9 from errata https://www.ti.com/lit/pdf/sprz334). How is this currently being handled in your system?

Regards,
Kevin

Kevin,

We'll expand the list of registers being dumped and should have an update for you in the next few days. And while there is a comment in the code about Advisory 9 from the silicon errata, we are still looking at the code to determine how it was handled.

Thanks,
Rob

Kevin,

We're still reviewing the code to determine how Advisory 9 is being handled; it's not clear. In the meantime, here are updated DDR3 register dumps — now including the PHY configuration registers.

From a working board (same as previously dumped):

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x00000070   : CURR: 0x000000e0
      DDR_PERF_CNT_2       : ORIG: 0x0000004c   : CURR: 0x00000098
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0xb1c278ba   : CURR: 0x1bf262c6
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0xad7ff7d7
      DDR_CFG 0x408   : 0x2b75b17f
      DDR_CFG 0x40c   : 0x4cfd7b57
      DDR_CFG 0x410   : 0x37fe775b
      DDR_CFG 0x414   : 0x574b7fdb
      DDR_CFG 0x418   : 0x5ddd1737
      DDR_CFG 0x41c   : 0x5f37b53f
      DDR_CFG 0x420   : 0xffd7bf92
      DDR_CFG 0x424   : 0xdd379f59
      DDR_CFG 0x428   : 0x7f7c1757
      DDR_CFG 0x42c   : 0x1b9507f5
      DDR_CFG 0x430   : 0x7b66d65f
      DDR_CFG 0x434   : 0xb5f675fb
      DDR_CFG 0x438   : 0xde6ce5f5
      DDR_CFG 0x43c   : 0xd38fcfaf
      DDR_CFG 0x440   : 0x0dfff73f
      DDR_CFG 0x444   : 0xee7f471f
      DDR_CFG 0x448   : 0x7b65e271
      DDR_CFG 0x44c   : 0x7feb6afd
      DDR_CFG 0x450   : 0xdd7d777b
      DDR_CFG 0x454   : 0xbd4f2daf
      DDR_CFG 0x458   : 0xca37cd6c
      DDR_CFG 0x45c   : 0xec3f77f7
      DDR_CFG 0x460   : 0xfefd5ab5
      DDR_CFG 0x464   : 0x1fd51f7c
      DDR_CFG 0x468   : 0x0d3e9f6c
      DDR_CFG 0x46c   : 0xdf6b379f
      DDR_CFG 0x470   : 0x355fecff
      DDR_CFG 0x474   : 0x3f3ef7ff
      DDR_CFG 0x478   : 0x3ef777fd
      DDR_CFG 0x47c   : 0x3bfffefe
      DDR_CFG 0x480   : 0x155fdc8d
      DDR_CFG 0x484   : 0x4a73efcf
      DDR_CFG 0x488   : 0xffd7d75f
      DDR_CFG 0x48c   : 0xfbdf7fdb
      DDR_CFG 0x490   : 0x109f4e8d
      DDR_CFG 0x494   : 0xffce4e75
      DDR_CFG 0x498   : 0xe7cb77f5
      DDR_CFG 0x49c   : 0x28c57faf
      DDR_CFG 0x4a0   : 0x33dfb3d6
      DDR_CFG 0x4a4   : 0xbfb5ebff
      DDR_CFG 0x4a8   : 0x53779975
      DDR_CFG 0x4ac   : 0x29f7696e
      DDR_CFG 0x4b0   : 0xffdf5eff
      DDR_CFG 0x4b4   : 0xd5dc3fff
      DDR_CFG 0x4b8   : 0x1f7ecffe
      DDR_CFG 0x4bc   : 0xffc737ff
      DDR_CFG 0x4c0   : 0xf35bc7fe
      DDR_CFG 0x4c4   : 0xfb539f6f
      DDR_CFG 0x4c8   : 0x5fa78ddf
      DDR_CFG 0x4cc   : 0x55c76ff7
      DDR_CFG 0x4d0   : 0xe3efb5bd
      DDR_CFG 0x4d4   : 0x53dbe47d
      DDR_CFG 0x4d8   : 0xc3ffe06e
      DDR_CFG 0x4dc   : 0xf2dff36f
      DDR_CFG 0x4e0   : 0x57fd57bb
      DDR_CFG 0x4e4   : 0x3ffd39f9
      DDR_CFG 0x4e8   : 0x37f7ffbe
      DDR_CFG 0x4ec   : 0x5fde77fb
      DDR_CFG 0x4f0   : 0xdbfeb5fc
      DDR_CFG 0x4f4   : 0xea5f673f

And from a failing board (also the same as previously dumped):

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000064   : CURR: 0x40000064
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x0000001d   : CURR: 0x0000003a
      DDR_PERF_CNT_2       : ORIG: 0x00000014   : CURR: 0x00000028
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x02d65cb1   : CURR: 0x02ef8c35
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x00000000
      DDR_CFG 0x408   : 0x00000000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000000
      DDR_CFG 0x428   : 0x00000000
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x00000000
      DDR_CFG 0x438   : 0x00000000
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x00000000
      DDR_CFG 0x458   : 0x00000000
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x00000000
      DDR_CFG 0x464   : 0x02000000
      DDR_CFG 0x468   : 0x00000000
      DDR_CFG 0x46c   : 0x00000000
      DDR_CFG 0x470   : 0x00000000
      DDR_CFG 0x474   : 0x02000000
      DDR_CFG 0x478   : 0x00000000
      DDR_CFG 0x47c   : 0x00000000
      DDR_CFG 0x480   : 0x02000000
      DDR_CFG 0x484   : 0x00000000
      DDR_CFG 0x488   : 0x00000000
      DDR_CFG 0x48c   : 0x00000000
      DDR_CFG 0x490   : 0x02000000
      DDR_CFG 0x494   : 0x00000000
      DDR_CFG 0x498   : 0x02000000
      DDR_CFG 0x49c   : 0x00000000
      DDR_CFG 0x4a0   : 0x02000000
      DDR_CFG 0x4a4   : 0x00000000
      DDR_CFG 0x4a8   : 0x00000000
      DDR_CFG 0x4ac   : 0x00000000
      DDR_CFG 0x4b0   : 0x00000000
      DDR_CFG 0x4b4   : 0x00000000
      DDR_CFG 0x4b8   : 0x00000000
      DDR_CFG 0x4bc   : 0x00000000
      DDR_CFG 0x4c0   : 0x00000000
      DDR_CFG 0x4c4   : 0x00000000
      DDR_CFG 0x4c8   : 0x00000000
      DDR_CFG 0x4cc   : 0x00000000
      DDR_CFG 0x4d0   : 0x02000000
      DDR_CFG 0x4d4   : 0x00000000
      DDR_CFG 0x4d8   : 0x00000000
      DDR_CFG 0x4dc   : 0x00000000
      DDR_CFG 0x4e0   : 0x00000000
      DDR_CFG 0x4e4   : 0x00000000
      DDR_CFG 0x4e8   : 0x00000000
      DDR_CFG 0x4ec   : 0x00000000
      DDR_CFG 0x4f0   : 0x00000000
      DDR_CFG 0x4f4   : 0x00000000

There are stark differences in the contents of the PHY configuration registers; do these dynamically change during the leveling processes?

Thanks,
Rob

Hi Rob,

Robert Reed said:

PHY configuration registers; do these dynamically change during the leveling processes?

I don't think all of the registers should change dynamically. For instance, DDR3_CONFIG_3 looks like a register that would be static. From my DDR PHY experience on other TI SOCs, init ratios don't usually change. (I unfortunately was not involved with this specific SOC though). 

Looking at the values provided from the working board, I am having difficulty mapping them to the documentation.

Using the example of DDR3_CONFIG_3, it looks like the upper 12 bits are set to a non-zero value, but the documentation shows them as reserved and with a reset value of 0x0. And the lower 20 bits of the same register don't match what I might have expected. 

Can you double check:

1. That the PHY registers are getting read from the correct SOC memory location? 
2. How the values read back correlate to the values programmed?

Thanks,
Kevin

~~~~~~~~~~~~~~~~~~~~~~~~~~

DDR_CFG 0x410   : 0x37fe775b

We've rechecked the register dump code, and it looks sound (it's a simple loop generating the register addresses to read). But in checking it we saw that the configuration registers of the working board changed from one dump to the next.

The configuration register dump code:

for (i = 0; i < 61; i++)
  {
	  snprintf(BIT_msg, BIT_MSG_SIZE, "      DDR_CFG 0x%03x   : 0x%08x\r\n", ((unsigned int)(0x404 + (i * 4))) , (*(unsigned int*)(0x21000000 + 0x00000404 + (i * 4)))         );  UART_Write(UART_RS232, (Uint8 *)BIT_msg);
  }
  
  snprintf(BIT_msg, BIT_MSG_SIZE, "\r\n\r\n");  UART_Write(UART_RS232, (Uint8 *)BIT_msg);

Dump 1:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x000001ca   : CURR: 0x0000023a
      DDR_PERF_CNT_2       : ORIG: 0x0000015e   : CURR: 0x000001aa
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x47824388   : CURR: 0x753463a7
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0xa31f1302
      DDR_CFG 0x408   : 0x23153316
      DDR_CFG 0x40c   : 0x024f2256
      DDR_CFG 0x410   : 0x034d5248
      DDR_CFG 0x414   : 0x464b530a
      DDR_CFG 0x418   : 0x1a4d020f
      DDR_CFG 0x41c   : 0x132f070e
      DDR_CFG 0x420   : 0x43158b10
      DDR_CFG 0x424   : 0x92139b52
      DDR_CFG 0x428   : 0x52551314
      DDR_CFG 0x42c   : 0x03170237
      DDR_CFG 0x430   : 0x023d021c
      DDR_CFG 0x434   : 0x063f637a
      DDR_CFG 0x438   : 0x023d423c
      DDR_CFG 0x43c   : 0xc31f0a3e
      DDR_CFG 0x440   : 0x0761132b
      DDR_CFG 0x444   : 0x022b432b
      DDR_CFG 0x448   : 0x43252264
      DDR_CFG 0x44c   : 0x46a70227
      DDR_CFG 0x450   : 0x132d0338
      DDR_CFG 0x454   : 0x232b032b
      DDR_CFG 0x458   : 0x023d022c
      DDR_CFG 0x45c   : 0x6a2f162e
      DDR_CFG 0x460   : 0x12354a34
      DDR_CFG 0x464   : 0x03331b32
      DDR_CFG 0x468   : 0x06351b34
      DDR_CFG 0x46c   : 0x0f371637
      DDR_CFG 0x470   : 0x127d0af8
      DDR_CFG 0x474   : 0x133f033b
      DDR_CFG 0x478   : 0x0e7d067d
      DDR_CFG 0x47c   : 0x133f427e
      DDR_CFG 0x480   : 0x034142c1
      DDR_CFG 0x484   : 0x424306c2
      DDR_CFG 0x488   : 0x03454645
      DDR_CFG 0x48c   : 0x0a475247
      DDR_CFG 0x490   : 0x12cb46c8
      DDR_CFG 0x494   : 0x43cb024b
      DDR_CFG 0x498   : 0x424d034d
      DDR_CFG 0x49c   : 0x024f0bcf
      DDR_CFG 0x4a0   : 0x02d722d6
      DDR_CFG 0x4a4   : 0x83738253
      DDR_CFG 0x4a8   : 0x02571355
      DDR_CFG 0x4ac   : 0x02f74256
      DDR_CFG 0x4b0   : 0x9e5b42d8
      DDR_CFG 0x4b4   : 0x575f037b
      DDR_CFG 0x4b8   : 0x035f03dc
      DDR_CFG 0x4bc   : 0x46df33de
      DDR_CFG 0x4c0   : 0x136943e0
      DDR_CFG 0x4c4   : 0x53630762
      DDR_CFG 0x4c8   : 0x02e587f5
      DDR_CFG 0x4cc   : 0x46674767
      DDR_CFG 0x4d0   : 0x026d1279
      DDR_CFG 0x4d4   : 0x536b066e
      DDR_CFG 0x4d8   : 0xc36d826c
      DDR_CFG 0x4dc   : 0x126f136e
      DDR_CFG 0x4e0   : 0x127117f3
      DDR_CFG 0x4e4   : 0x327b1272
      DDR_CFG 0x4e8   : 0x32f7537c
      DDR_CFG 0x4ec   : 0x567703f6
      DDR_CFG 0x4f0   : 0x43fd0378
      DDR_CFG 0x4f4   : 0x627b037b

Dump 2:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x00000070   : CURR: 0x000000e0
      DDR_PERF_CNT_2       : ORIG: 0x0000004c   : CURR: 0x00000098
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x5b5c4004   : CURR: 0x886305a7
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0xbf7f77d7
      DDR_CFG 0x408   : 0x2b75b37f
      DDR_CFG 0x40c   : 0x4eff7b57
      DDR_CFG 0x410   : 0x37ff575b
      DDR_CFG 0x414   : 0x574b7fdb
      DDR_CFG 0x418   : 0x5bddb727
      DDR_CFG 0x41c   : 0x5f3fb73f
      DDR_CFG 0x420   : 0xffd7bf92
      DDR_CFG 0x424   : 0xf7b79f5b
      DDR_CFG 0x428   : 0x7f7d17d7
      DDR_CFG 0x42c   : 0x9b9717f7
      DDR_CFG 0x430   : 0x7b7fd65e
      DDR_CFG 0x434   : 0xb7ff77fb
      DDR_CFG 0x438   : 0x9f7ceffc
      DDR_CFG 0x43c   : 0xd33fcfef
      DDR_CFG 0x440   : 0x0ffff73f
      DDR_CFG 0x444   : 0xef7f473f
      DDR_CFG 0x448   : 0xfb67e375
      DDR_CFG 0x44c   : 0x7fef6b7f
      DDR_CFG 0x450   : 0xff7d7f7f
      DDR_CFG 0x454   : 0xbf4f2daf
      DDR_CFG 0x458   : 0xda3fef6c
      DDR_CFG 0x45c   : 0xee3f77ff
      DDR_CFG 0x460   : 0xfbfd5ab5
      DDR_CFG 0x464   : 0x1ff71f7f
      DDR_CFG 0x468   : 0x2f3f9f64
      DDR_CFG 0x46c   : 0xdf3f37bf
      DDR_CFG 0x470   : 0x377fccff
      DDR_CFG 0x474   : 0x3f3fffff
      DDR_CFG 0x478   : 0x3e7f57fd
      DDR_CFG 0x47c   : 0x3bfffe7e
      DDR_CFG 0x480   : 0x175fdfcd
      DDR_CFG 0x484   : 0x4e73efcb
      DDR_CFG 0x488   : 0xffc7d75f
      DDR_CFG 0x48c   : 0xfbdf7fcb
      DDR_CFG 0x490   : 0x10db4ecd
      DDR_CFG 0x494   : 0xffcf4eff
      DDR_CFG 0x498   : 0xc7cf73fd
      DDR_CFG 0x49c   : 0x29c77fff
      DDR_CFG 0x4a0   : 0x33dfb3d6
      DDR_CFG 0x4a4   : 0xbff7ebff
      DDR_CFG 0x4a8   : 0x53f79bf5
      DDR_CFG 0x4ac   : 0x2bf76bfe
      DDR_CFG 0x4b0   : 0xffdf5eff
      DDR_CFG 0x4b4   : 0xd7df3fff
      DDR_CFG 0x4b8   : 0x3f7fcffe
      DDR_CFG 0x4bc   : 0xffcf3fff
      DDR_CFG 0x4c0   : 0xf37bc7fe
      DDR_CFG 0x4c4   : 0xdbf39f6f
      DDR_CFG 0x4c8   : 0x5fe7c7ff
      DDR_CFG 0x4cc   : 0x57e7e7f7
      DDR_CFG 0x4d0   : 0xf3efb7bd
      DDR_CFG 0x4d4   : 0x53fbe67f
      DDR_CFG 0x4d8   : 0xe3eff36e
      DDR_CFG 0x4dc   : 0xf2dff36f
      DDR_CFG 0x4e0   : 0x57fd57fb
      DDR_CFG 0x4e4   : 0x37fd3bfb
      DDR_CFG 0x4e8   : 0x37f7fffe
      DDR_CFG 0x4ec   : 0x5fff77ff
      DDR_CFG 0x4f0   : 0xdbffb7fe
      DDR_CFG 0x4f4   : 0xea7f67ff

Dump 3:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x00000070   : CURR: 0x000000e0
      DDR_PERF_CNT_2       : ORIG: 0x0000004c   : CURR: 0x00000098
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x18c22ee9   : CURR: 0x45c3cd91
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0xbffff7d7
      DDR_CFG 0x408   : 0xab77f37f
      DDR_CFG 0x40c   : 0x6eff7b7f
      DDR_CFG 0x410   : 0x37ff775f
      DDR_CFG 0x414   : 0x576b7fdb
      DDR_CFG 0x418   : 0x7fddb7f7
      DDR_CFG 0x41c   : 0x5f3fb7ff
      DDR_CFG 0x420   : 0xffd7bfda
      DDR_CFG 0x424   : 0xffb7bfdb
      DDR_CFG 0x428   : 0x7ffd17d7
      DDR_CFG 0x42c   : 0xdf9757f7
      DDR_CFG 0x430   : 0x7b7edf5e
      DDR_CFG 0x434   : 0xb7fffffb
      DDR_CFG 0x438   : 0xdf6ceffd
      DDR_CFG 0x43c   : 0xdbbfcfef
      DDR_CFG 0x440   : 0x9ffff73f
      DDR_CFG 0x444   : 0xffffdfbf
      DDR_CFG 0x448   : 0xff67f77d
      DDR_CFG 0x44c   : 0x7fefef7f
      DDR_CFG 0x450   : 0xff7f7fff
      DDR_CFG 0x454   : 0xbf4f7def
      DDR_CFG 0x458   : 0xfa3fef6d
      DDR_CFG 0x45c   : 0xfe3ff7ff
      DDR_CFG 0x460   : 0xfffddad5
      DDR_CFG 0x464   : 0x1ff79fff
      DDR_CFG 0x468   : 0x2fbfdffe
      DDR_CFG 0x46c   : 0xdf3f77bf
      DDR_CFG 0x470   : 0x37ffecff
      DDR_CFG 0x474   : 0x3fffffff
      DDR_CFG 0x478   : 0x7fff7ffd
      DDR_CFG 0x47c   : 0x3bfffefe
      DDR_CFG 0x480   : 0xd77fdfed
      DDR_CFG 0x484   : 0x7e73efef
      DDR_CFG 0x488   : 0xffdfff5f
      DDR_CFG 0x48c   : 0xffdfffdb
      DDR_CFG 0x490   : 0x11db5ecd
      DDR_CFG 0x494   : 0xffcf5eff
      DDR_CFG 0x498   : 0xe7cf7ffd
      DDR_CFG 0x49c   : 0x29cf7fff
      DDR_CFG 0x4a0   : 0x37ffbff6
      DDR_CFG 0x4a4   : 0xbfffebff
      DDR_CFG 0x4a8   : 0xd3ff9bf7
      DDR_CFG 0x4ac   : 0x3bf7fbfe
      DDR_CFG 0x4b0   : 0xffdf5eff
      DDR_CFG 0x4b4   : 0xf7df3fff
      DDR_CFG 0x4b8   : 0x7f7feffe
      DDR_CFG 0x4bc   : 0xffcf3fff
      DDR_CFG 0x4c0   : 0xfb7fcffe
      DDR_CFG 0x4c4   : 0xfbf3dfef
      DDR_CFG 0x4c8   : 0x5fefcfff
      DDR_CFG 0x4cc   : 0x57e7eff7
      DDR_CFG 0x4d0   : 0xf3eff7bf
      DDR_CFG 0x4d4   : 0x53fbe6fd
      DDR_CFG 0x4d8   : 0xf3fff37f
      DDR_CFG 0x4dc   : 0xf2fff37f
      DDR_CFG 0x4e0   : 0xfffdffff
      DDR_CFG 0x4e4   : 0x7ffdfbff
      DDR_CFG 0x4e8   : 0x37ffffff
      DDR_CFG 0x4ec   : 0x5ffff7ff
      DDR_CFG 0x4f0   : 0xdffff7fe
      DDR_CFG 0x4f4   : 0xee7f7fff

We're still looking at the Advisory 9 code, trying to understand it.

OK, we think we were using the wrong base address for dumping the PHY configuration registers. Here's the new code:

  for (i = 0; i < 61; i++)
  {
	  snprintf(BIT_msg, BIT_MSG_SIZE, "      DDR_CFG 0x%03x   : 0x%08x\r\n", ((unsigned int)(0x404 + (i * 4))) , (*(unsigned int*)(0x02620000 + 0x00000404 + (i * 4)))         );  UART_Write(UART_RS232, (Uint8 *)BIT_msg);
  }
  
  snprintf(BIT_msg, BIT_MSG_SIZE, "\r\n\r\n");  UART_Write(UART_RS232, (Uint8 *)BIT_msg);

And some new dumps from the working board using the 0x02620000 base address. They are much more consistent, which is in line with what you said about (most of) the configuration registers not changing dynamically. I'll post a comparison with the values loaded as soon as I can locate the relevant code

Dump 1:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x00000070   : CURR: 0x000000e0
      DDR_PERF_CNT_2       : ORIG: 0x0000004c   : CURR: 0x00000098
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x14971f04   : CURR: 0x55d4a78e
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020117f
      DDR_CFG 0x408   : 0x01002000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ff000
      DDR_CFG 0x438   : 0x03b96c1f
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

Dump 2:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x000000e0   : CURR: 0x00000150
      DDR_PERF_CNT_2       : ORIG: 0x00000098   : CURR: 0x000000e4
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x0636a370   : CURR: 0x33e206dc
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020007f
      DDR_CFG 0x408   : 0x01000000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ff000
      DDR_CFG 0x438   : 0x0479f07c
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

Dump 3:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x00000070   : CURR: 0x000000e0
      DDR_PERF_CNT_2       : ORIG: 0x0000004c   : CURR: 0x00000098
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x4a80bb53   : CURR: 0x778d34b8
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020047f
      DDR_CFG 0x408   : 0x0100a000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ff000
      DDR_CFG 0x438   : 0x03e08c27
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

Dump 4:

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000004   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x00000070   : CURR: 0x000000e0
      DDR_PERF_CNT_2       : ORIG: 0x0000004c   : CURR: 0x00000098
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x82fc9b47   : CURR: 0xc430bdb2
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020007f
      DDR_CFG 0x408   : 0x01000000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ff000
      DDR_CFG 0x438   : 0x0459f07f
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

And now for the configuration register dumps from a failing board (same one as previously posted).

Dump 1

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000064   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x0000001d   : CURR: 0x0000003a
      DDR_PERF_CNT_2       : ORIG: 0x00000014   : CURR: 0x00000028
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x105827c9   : CURR: 0x11bc615c
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020047f
      DDR_CFG 0x408   : 0x01000000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ff000
      DDR_CFG 0x438   : 0x01b94c74
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

Dump 2

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000064   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x0000003a   : CURR: 0x00000057
      DDR_PERF_CNT_2       : ORIG: 0x00000028   : CURR: 0x0000003c
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x488ced60   : CURR: 0x49491447
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020007f
      DDR_CFG 0x408   : 0x0100a000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ee000
      DDR_CFG 0x438   : 0x01b86c3f
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

Dump 3

      DDR_MIDR             : ORIG: 0x40466400   : CURR: 0x40466400
      DDR_STATUS           : ORIG: 0x40000064   : CURR: 0x40000004
      DDR_SDCFG            : ORIG: 0x6307bb32   : CURR: 0x6307bb32
      DDR_SDRFC            : ORIG: 0x20001860   : CURR: 0x20001860
      DDR_SDTIM1           : ORIG: 0x1557b9bd   : CURR: 0x1557b9bd
      DDR_SDTIM2           : ORIG: 0x40d7a02b   : CURR: 0x40d7a02b
      DDR_SDTIM3           : ORIG: 0x559f8cff   : CURR: 0x559f8cff
      DDR_PMCTL            : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_LAT_CONFIG       : ORIG: 0x00ffffff   : CURR: 0x00ffffff
      DDR_PERF_CNT_1       : ORIG: 0x0000001d   : CURR: 0x0000003a
      DDR_PERF_CNT_2       : ORIG: 0x00000014   : CURR: 0x00000028
      DDR_PERF_CNT_CFG     : ORIG: 0x00010000   : CURR: 0x00010000
      DDR_PERF_CNT_SEL     : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_PERF_CNT_TIM     : ORIG: 0x3133bac5   : CURR: 0x361bc1e4
      DDR_IRQSTATUS_RAW_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQSTATUS_SYS    : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_SET_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_IRQENABLE_CLR_SYS: ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ZQCONFIG         : ORIG: 0x70073214   : CURR: 0x70073214
      DDR_RDWR_LVL_RMP_CTRL: ORIG: 0x80030300   : CURR: 0x80030300
      DDR_RDWR_LVL_CTRL    : ORIG: 0x7f090900   : CURR: 0x7f090900
      DDR_DDRPHYC          : ORIG: 0x0010010f   : CURR: 0x0010010f
      DDR_PRI_COS_MAP      : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_1_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_MSTID_COS_2_MAP  : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCCTL           : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR1         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_ECCADDR2         : ORIG: 0x00000000   : CURR: 0x00000000
      DDR_RWTHRESH         : ORIG: 0x00000305   : CURR: 0x00000305
      DDR_CFG 0x404   : 0x6020107f
      DDR_CFG 0x408   : 0x01000000
      DDR_CFG 0x40c   : 0x00000000
      DDR_CFG 0x410   : 0x00000000
      DDR_CFG 0x414   : 0x00000000
      DDR_CFG 0x418   : 0x00000000
      DDR_CFG 0x41c   : 0x00000000
      DDR_CFG 0x420   : 0x00000000
      DDR_CFG 0x424   : 0x00000048
      DDR_CFG 0x428   : 0x0000003f
      DDR_CFG 0x42c   : 0x00000000
      DDR_CFG 0x430   : 0x00000000
      DDR_CFG 0x434   : 0x0a0ff000
      DDR_CFG 0x438   : 0x01ba1c77
      DDR_CFG 0x43c   : 0x00000000
      DDR_CFG 0x440   : 0x00000000
      DDR_CFG 0x444   : 0x00000000
      DDR_CFG 0x448   : 0x00000000
      DDR_CFG 0x44c   : 0x00000000
      DDR_CFG 0x450   : 0x00000000
      DDR_CFG 0x454   : 0x0000008e
      DDR_CFG 0x458   : 0x00000097
      DDR_CFG 0x45c   : 0x00000000
      DDR_CFG 0x460   : 0x0a619834
      DDR_CFG 0x464   : 0x0000015b
      DDR_CFG 0x468   : 0x00841d8c
      DDR_CFG 0x46c   : 0x00000019
      DDR_CFG 0x470   : 0x00841d8c
      DDR_CFG 0x474   : 0x0000001b
      DDR_CFG 0x478   : 0x00841d8c
      DDR_CFG 0x47c   : 0x0000001d
      DDR_CFG 0x480   : 0x00841d8c
      DDR_CFG 0x484   : 0x0000001f
      DDR_CFG 0x488   : 0x00841d8c
      DDR_CFG 0x48c   : 0x00000021
      DDR_CFG 0x490   : 0x00841d8c
      DDR_CFG 0x494   : 0x00000023
      DDR_CFG 0x498   : 0x00841d8c
      DDR_CFG 0x49c   : 0x00000025
      DDR_CFG 0x4a0   : 0x00841d8c
      DDR_CFG 0x4a4   : 0x00000027
      DDR_CFG 0x4a8   : 0x00841d8c
      DDR_CFG 0x4ac   : 0x00000029
      DDR_CFG 0x4b0   : 0x00841d8c
      DDR_CFG 0x4b4   : 0x0000002b
      DDR_CFG 0x4b8   : 0x00841d8c
      DDR_CFG 0x4bc   : 0x0000002d
      DDR_CFG 0x4c0   : 0x00841d8c
      DDR_CFG 0x4c4   : 0x0000002f
      DDR_CFG 0x4c8   : 0x00841d8c
      DDR_CFG 0x4cc   : 0x00000031
      DDR_CFG 0x4d0   : 0x00841d8c
      DDR_CFG 0x4d4   : 0x00000033
      DDR_CFG 0x4d8   : 0x00841d8c
      DDR_CFG 0x4dc   : 0x00000035
      DDR_CFG 0x4e0   : 0x00841d8c
      DDR_CFG 0x4e4   : 0x00000037
      DDR_CFG 0x4e8   : 0x00841d8c
      DDR_CFG 0x4ec   : 0x00000039
      DDR_CFG 0x4f0   : 0x00841d8c
      DDR_CFG 0x4f4   : 0x0000003b

And here's what I've been able to piece together so far about the values originally written into the PHY configuration registers:

I've finally determined that our code is implementing workaround #3 for Silicon Errata #9, incremental read eye leveling. This is correct for our hardware which is using revision 2.0 silicon. The critical sections of code implement the following:

  RDWR_LVL_RMP_CTRL = 0x80000000;
  RDWR_LVL_CTRL = 0x80000000;
  TIME_SoftWait(7000);

  RDWR_LVL_RMP_WIN = 0x00000502;
  RDWR_LVL_RMP_CTRL = 0x80030300;
  RDWR_LVL_CTRL = 0xFF090900;

Since all but bit 31 (RDWR_LVL_EN) of RDWR_LVL_RMP_CTRL is reserved, I don't know what the significance of the remaining bits equaling 0x00030300 instead of 0x0 is on a Keystone I device is. And I'm now trying to determine how the settings for RDWRLVLINC_PRE (= 0xFF), RDLVLINC_INT (= 0x9), and RDLVLGATEINC_INT (=0x9) were arrived at.

Bump.

Robert Reed said:

I've finally determined that our code is implementing workaround #3 for Silicon Errata #9, incremental read eye leveling

Hi Robert,

Thanks - are you able to try workaround #1 (set bit 9 in DDR3_CONFIG_23) to see if it has any impact on the failure? It may be worthwhile given that the bad board was showing a failure for read training. I remember you previously mentioning that the flash was programmed off board. Is this still a limitation? 

I tried comparing your dump #1 from both the good and bad system, but differences in the controller registers were only in the performance counter registers, and I did not quite make sense of some of the PHY values read out compared to documentation. 

Regards,
Kevin

Kevin,

We'll give it try. While I was poking around in the code trying to determine which Advisory 9 workaround was in use, I did run across this bit of commented-out code indicating that there probably was an attempt made to use workaround #1 but that it was abandoned for some reason.

  // **************** 3.0 Leveling Register Configuration ********************/
  // Using partial automatic leveling due to errata */

  // **************** 3.2 Invert Clock Out ********************/
  DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
  DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
  DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
  DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15

  //  DDR3_CONFIG_REG_23 &= 0xC0000000; // clear bits, leaving reserved bits

  //  DDR3_CONFIG_REG_23 = (0x34 << 0) | //RD_DQS SLAVE RATIO
  //      (0x85 << 10)             | //WR_DQS SLAVE RATIO
  //      (0xC5 << 20);              // WR DATA_DQS SLAVE RATIO
  //  DDR3_CONFIG_REG_24 = (0xDB << 0); //FIFO_DQS SLAVE RATIO

  //Values with invertclkout = 1
  // **************** 3.3+3.4 Partial Automatic Leveling ********************/
  DATA0_WRLVL_INIT_RATIO = 0x00;
  DATA1_WRLVL_INIT_RATIO = 0x00;
  DATA2_WRLVL_INIT_RATIO = 0x00;
  DATA3_WRLVL_INIT_RATIO = 0x00;
  DATA4_WRLVL_INIT_RATIO = 0x00;
  DATA5_WRLVL_INIT_RATIO = 0x00;
  DATA6_WRLVL_INIT_RATIO = 0x40;
  DATA7_WRLVL_INIT_RATIO = 0x40;
  DATA8_WRLVL_INIT_RATIO = 0x00;

  DATA0_GTLVL_INIT_RATIO = 0x00;
  DATA1_GTLVL_INIT_RATIO = 0x00;
  DATA2_GTLVL_INIT_RATIO = 0x00;
  DATA3_GTLVL_INIT_RATIO = 0x00;
  DATA4_GTLVL_INIT_RATIO = 0x00;
  DATA5_GTLVL_INIT_RATIO = 0x00;
  DATA6_GTLVL_INIT_RATIO = 0x8F;
  DATA7_GTLVL_INIT_RATIO = 0x8F;
  DATA8_GTLVL_INIT_RATIO = 0x00;

  // Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
  DDR_DDRPHYC &= ~(0x00008000);
  DDR_DDRPHYC |= (0x00008000);
  DDR_DDRPHYC &= ~(0x00008000);

This is the only mention of DDR3_CONFIG_REG_23 in the code I've been able to find to date, so it looks like the register is left in its default post-reset state and partial automatic leveling is disabled. Are there any clear examples of how to implement the Advisory 9 workarounds? We're picking through old code here, second-guessing at what was intended, and an explicit guide to how things should be done that we can work off of would be appreciated.

Which dumped PHY values are confusing to you? I can concentrate on those as I continue to dig.

We are still limited by the DSP DDR3 memory being needing to be operational to reflash the board, unfortunately. I'm increasingly unsure if any earlier development code without this limitation exists; it's possible the prototypes used a ZIF socket for the flash and it's always been this way.

Bump.

Robert,

Is the code you're referencing from the TI provided SDK?  Or is that your modified version?

If it's from the SDK ... unfortunately we don't have the history on these code changes over time.

Regards,

Kyle

Kyle,

The code is ours, and we're in the same bind. We don't know why the code was commented out, but since it's the only reference to DDR3_CONFIG_REG_23 in our code we have to assume that our code hasn't made any change to the default value.

Bump.

Bump.

Bump.

Hi Robert,

Robert Reed said:

Are there any clear examples of how to implement the Advisory 9 workarounds? We're picking through old code here, second-guessing at what was intended, and an explicit guide to how things should be done that we can work off of would be appreciated.

No, I am not aware of any specific example. But the way I read the errata is that the only difference from normal auto leveling is that you just enable bit 9 of DDR3_CONFIG_REG_23. Essentially, bit 9 will act as a mask to prevent the read data eye training from occurring. So I would assume you only need to add one line of code (to enable bit 9 of REG_23).

This mode is enabled by setting bit 9 (0-indexed) of the DDR3_CONFIG_REG_23 at address 0x02620460. The lower 8 bits (bits 7:0) must not be overwritten and will contain their default value of 0x34 . The default value is recommended for use. After programming DDR3_CONFIG_REG_23, proceed to enable auto-leveling. Please refer to the DDR3 Initialization Application Report (SPRABL2) for details of the sequence of steps.

http://www.ti.com/lit/pdf/SPRABL2

Regards,
Kevin