TDA4VM: clock of PCIe_M.2

Hi Zhang,

Could you try out the patches in the FAQ referenced in this E2E: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1003494/processor-sdk-j721e-how-can-i-configure-pcie-controllers-0-and-1-for-internal-clocks.

REFCLK2 and ACSPCIe1 that are used by PCIe2 should be configured by this patch to use the internal refclk instead of external refclk.

Regards,

Takuma

HI Takuma,

    Thinks for your support. we  have tried patches on sdk 08_06_00_11, but it failed. the log as follows:

patch < pcie-ref-clock-out_sdk8.diff 
(Stripping trailing CRs from patch; use --binary to disable.)
patching file phy-cadence-sierra.c
Hunk #1 succeeded at 236 with fuzz 2 (offset 66 lines).
Hunk #2 FAILED at 273.
Hunk #3 succeeded at 521 with fuzz 1 (offset 170 lines).
Hunk #4 FAILED at 678.
Hunk #5 succeeded at 1054 with fuzz 2 (offset 368 lines).
Hunk #6 succeeded at 1082 with fuzz 2 (offset 335 lines).
patch: **** malformed patch at line 139: +	/* PCIE_REFCLK3_CLKSEL : EN + SERDES1_REF_DER_OUT_CLK */

can you  give us some suggestions 

Hi Davied,

I went through 8.6 SDK and it seems like most of what the patch enables is already there. I think the only piece that is missing in the SDK, is

• Enables differential clock buffers ACSPCIe
• Select SERDES output as the input to the clock buffers

from the patches that my colleague Jian posted.

I extracted this portion from the patches and created a new patch:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_enable_2D00_tda4vm_2D00_pcie_2D00_internal_2D00_refclk.patch

Could you try applying this new patch?

Regards,

Takuma

Hi，Takuma

    Thinks for your support. We have patched 0001-enable-tda4vm-pcie-internal-refclk.patch, and rebuild sdk. But it doesn't work. the log as follows:

root@j7-evm:~# dmesg |grep pcie
[    1.206578] j721e-pcie 2900000.pcie: host bridge /bus@100000/pcie@2900000 ranges:
[    1.214252] j721e-pcie 2900000.pcie:       IO 0x0010001000..0x0010010fff -> 0x0010001000
[    1.222529] j721e-pcie 2900000.pcie:      MEM 0x0010011000..0x0017ffffff -> 0x0010011000
[    1.230805] j721e-pcie 2900000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    2.250167] j721e-pcie 2900000.pcie: PCI host bridge to bus 0000:00
[    2.353792] pcieport 0000:00:00.0: PME: Signaling with IRQ 68
[    2.360173] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    2.367840] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    2.376115] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    2.384395] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    3.393042] j721e-pcie 2910000.pcie: PCI host bridge to bus 0001:00
[    3.472254] pcieport 0001:00:00.0: PME: Signaling with IRQ 71
[    3.478616] j721e-pcie 2920000.pcie: host bridge /bus@100000/pcie@2920000 ranges:
[    3.486293] j721e-pcie 2920000.pcie:       IO 0x4400001000..0x4400010fff -> 0x0000001000
[    3.494569] j721e-pcie 2920000.pcie:      MEM 0x4400011000..0x4407ffffff -> 0x0000011000
[    3.502845] j721e-pcie 2920000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    3.625944] j721e-pcie 2920000.pcie: Failed to init phy
[    3.631311] j721e-pcie: probe of 2920000.pcie failed with error -110

Hi，Takuma

     We have patched the 0001-enable-tda4vm-pcie-internal-refclk.patch, and test on TDA4VM EVM and SK-TDA4VM. It doesn't work.So we think that the patch can't solve this problem.  Could you help us verify this patch on sdk 08.06.00.11?

Hi Davied,

It may be that there is an issue elsewhere if the patch did not work. Could you tell me more about the setup?

1. Is the device connected on the M.2 slot something like a NVMe SSD? In which case TDA4VM would be RC and the SSD an EP device?
2. Could you verify in k3-j721e-common-proc-board.dts that pcie2_rc is not disabled? Please send over k3-j721e-common-proc-board.dts and k3-j721e-main.dtsi so that I can verify as well.
3. Could you send a picture of the board modifications that has been done? I would like to verify if the correct resistors have been removed and reinstalled.

Regards,

Takuma

Hi, Takuma

     Thinks for your support. Now we are test patch on TDA4EVM EVM not on our custom board, it don't work. the process is as follows:

1. Changes the CON_PCIE2_M2_REFCLK  from CLKGEN_SERDES2_REFCLK to SOC_SERDES2_REFCLK on the TDA4EVM.

2. Patch and rebulid sdk.

3. Copy  /lib/modules  to sdcard.

4. Start TDA4EVM 

SSD can be recognized before those changes.the log as follows:

root@j7-evm:~# dmesg |grep pcie
[    1.206745] j721e-pcie 2900000.pcie: host bridge /bus@100000/pcie@2900000 ranges:
[    1.214421] j721e-pcie 2900000.pcie:       IO 0x0010001000..0x0010010fff -> 0x0010001000
[    1.222697] j721e-pcie 2900000.pcie:      MEM 0x0010011000..0x0017ffffff -> 0x0010011000
[    1.230974] j721e-pcie 2900000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    2.250330] j721e-pcie 2900000.pcie: PCI host bridge to bus 0000:00
[    2.354019] pcieport 0000:00:00.0: PME: Signaling with IRQ 68
[    2.360394] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    2.368061] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    2.376337] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    2.384616] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    3.393266] j721e-pcie 2910000.pcie: PCI host bridge to bus 0001:00
[    3.472490] pcieport 0001:00:00.0: PME: Signaling with IRQ 71
[    3.478851] j721e-pcie 2920000.pcie: host bridge /bus@100000/pcie@2920000 ranges:
[    3.486524] j721e-pcie 2920000.pcie:       IO 0x4400001000..0x4400010fff -> 0x0000001000
[    3.494800] j721e-pcie 2920000.pcie:      MEM 0x4400011000..0x4407ffffff -> 0x0000011000
[    3.503075] j721e-pcie 2920000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    3.614326] j721e-pcie 2920000.pcie: Link up
[    3.618749] j721e-pcie 2920000.pcie: PCI host bridge to bus 0002:00
[    3.777133] pcieport 0002:00:00.0: enabling device (0000 -> 0002)

and we can find the ssd has been mounted.

/dev/nvme0n1p1  256M   32M  225M  13% /run/media/nvme0n1p1

Now we can't  drive pcie successfully.the log as follows:

root@j7-evm:~# dmesg |grep pcie
[    1.206578] j721e-pcie 2900000.pcie: host bridge /bus@100000/pcie@2900000 ranges:
[    1.214252] j721e-pcie 2900000.pcie:       IO 0x0010001000..0x0010010fff -> 0x0010001000
[    1.222529] j721e-pcie 2900000.pcie:      MEM 0x0010011000..0x0017ffffff -> 0x0010011000
[    1.230805] j721e-pcie 2900000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    2.250167] j721e-pcie 2900000.pcie: PCI host bridge to bus 0000:00
[    2.353792] pcieport 0000:00:00.0: PME: Signaling with IRQ 68
[    2.360173] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    2.367840] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    2.376115] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    2.384395] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    3.393042] j721e-pcie 2910000.pcie: PCI host bridge to bus 0001:00
[    3.472254] pcieport 0001:00:00.0: PME: Signaling with IRQ 71
[    3.478616] j721e-pcie 2920000.pcie: host bridge /bus@100000/pcie@2920000 ranges:
[    3.486293] j721e-pcie 2920000.pcie:       IO 0x4400001000..0x4400010fff -> 0x0000001000
[    3.494569] j721e-pcie 2920000.pcie:      MEM 0x4400011000..0x4407ffffff -> 0x0000011000
[    3.502845] j721e-pcie 2920000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    3.625944] j721e-pcie 2920000.pcie: Failed to init phy
[    3.631311] j721e-pcie: probe of 2920000.pcie failed with error -110

Could ou give us some suggestions？

Regards,

zhang

Hi Zhang,

I reproduced the issue on my EVM. It may take me a week or longer to root cause what the issue could be. My suspicion is that some of the registers being configured in the original patch is not being configured.

In the meantime, please let me know any debug that has been done on your end for enabling the internal clock.

Regards,

Takuma

Hi,Takuma

      Thinks for your support. 

     Sorry for the late reply，because We are debugging other modules. Has the issue been solved?

Regards,

Zhang

Hi Davied,

Apologies for the delay, debug is taking unexpectedly long on this one. 

I will need a few days more to get some better progress.

Regards, 

Takuma

Hi Davied,

Apologies for the late response and thank you for your patience. For 8.6 SDK, I am having some issues that I am still working through, but for 8.0 SDK I have got the internal refclks to be routed to PCIe.

On top of the patches in the FAQ, there needs to be a device tree change to select the core_ref_clk. In k3-j721e-main.dtsi, this core_ref_clk is selected by default, but there is an additional dts file that overwrites these default values in k3-j721e-common-proc-board.dts.

Commenting the wiz* section out in this additional dts file like below makes the link come up on my PCIe device:

Could you try out this change and post any logs if issues still persist?

Regards,

Takuma

Hi Davied,

I resolved the issue for 8.6 SDK as well and updated the FAQ with new patches. If you get the chance, please try them out and let me know if there are further issues:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004565/faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally

Regards,

Takuma