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Original question:

AM62A7-Q1: stripline of DDR design guideline

AM62A7-Q1: Some guidelines that cannot be followed in 6 layers

KenF
Expert 7150 points
Part Number: AM62A7-Q1

Hello Experts,

Our customer is building their own board. In the case of 6 layers, the following guidelines are unlikely to be adhered to.
- Internal wiring of main wiring (strip-line)
- Power supply (1.1V) plane for DRAM signal area
- Recommended wiring impedance

We heard in the E2E that strip-lines are recommended for EMI countermeasures, but not required. What are the adverse effects of not following the other two points?

Best regards,
Ken

  • +1
    TI__Guru**** 188639 points

    Hello Ken, 

    Thank you for the query.

    Please refer inputs i received from the expert.

    - Power supply (1.1V) plane for DRAM signal area
    >> Not following this guideline is likely to result in increased power supply noise. This will adversely impact signal integrity by resulting in reduction in the eye opening

    - Recommended wiring impedance
    >> Not adhering to this guideline is likely to result in greater signal reflections at both DRAM and SoC ends. This will adversely impact signal integrity by resulting in reduction in the eye opening.
    >> The optimum drive strength/ODT setting to get best results for read/write simulations might need to be modified appropriately, based on actual wiring impedance for signal traces.
    >> TI strongly recommends performing detailed signal integrity simulations as highlighted in the DDR design application note, to ensure that the pass/fail criteria at system-level are met.

    Regards,

    Sreenivasa