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AM3358: Spread Spectrum Clocking

Part Number: AM3358


One of our products uses a Beaglebone black (AM3358) to drive a 800 x 480 TFT display through a 18 bit RGB interface.

We have problem to meet the requirements of radiated emission levels.
We have managed reducing the radiated level by reducing the LCD clock from ~24MHz to ~11MHz but we cannot go any further as the refresh rate of the display becomes too slow.

I think spectrum spreading may help reducing the level (We would like to avoid modifying the PCB if possible).
Would it be possible to enable spectrum-spreading on the LCD clock by properly setting clock registers on the AM3358 ?

If yes, how to do it with Linux (Debian build) ?

Thanks for your help.

  • Someone pointed me to another E2E post where a similar topic was discussed. Please read the following E2E thread: AM3352: How to use Spread Spectrum Clocking function? - Processors forum - Processors - TI E2E support forums

    Let me know your PLL configuration, similar to what was discussed in the other thread. I will get JJD to calculate appropriate values for your use case. I will assign this thread to someone from our Linux team for details of how to apply the updated PLL configuration after we understand the appropriate values.

    Regards,
    Paul

  • Paul,

    Thanks for your reply, I think the configuration is similar to the post you mentioned and I agree good layout is the proper way to address the problem. Unfortunately, modifying the layout is not a practical option for us at the moment. The last test we did, we failed by 1.4dB at 94MHz, that is the reason why I though enabling the spectrum spreading on the AM3858 on the Beaglebone black controlling the display could allow reducing the level by few dB. Unfortunately, my knowledge of Debian and the Beaglebone is very limited and I would appreciate if somebody could help me to enable the spreading on the AM3858 to see if that could be a valid option. At this stage, as that is just for evaluation, maybe changes could be done through the terminal without rebuilding the kernel. 

    Regards

    Gilles

  • I'm not able to help with software. The first step is providing your current PLL configuration by dumping the register values discussed in other thread. I will ask James to calculate the register values required to enable SSC and reduce the level by about 2dB. We will send you the new register values. I can ask someone from the software team to provide guidance, but you will need to make the changes.

    Regards,
    Paul

  • Thanks for your reply.

    1) current PLL configuration:
    I am sorry but I need some guidance to dump the memory area corresponding to the PLL registers as my knowledge on linux is very limited.
    I have tried different commands like "hexdump" with no success, access denied to /dev/mem.

    2) U-Boot:
    I found on github the function "void set_mpu_spreadspectrum(int permille)" in the module clock_am33xx.c which seems used to set the spreading to 1.8%
    (https://github.com/beagleboard/u-boot/blob/master/arch/arm/mach-omap2/am33xx/clock_am33xx.c#L244).

    a) Is it possible to change the clock spreading while the kernel is running or has it to be set by the bootloader?
    Assuming I could get access to the PLL registers through the terminal, would it be possible to change them with a command to enable the clock spreading?

    b) What are the steps to get a bootloader setting the spectrum spreading? 

    Regards

    Gilles

     

  • The only question I can answer is the one where you are asking if the SSC configuration can be applied while the display subsystem is operational. The answer is no. The SSC configuration would need to be applied at the same time your software is currently initializing the PLL for the first time. The PLL must be configured to its final operating condition before you initialize the display subsystem.

    I will try to find someone from the software team that can answer your other questions. 

  • The SSC configuration would need to be applied at the same time your software is currently initializing the PLL for the first time. The PLL must be configured to its final operating condition before you initialize the display subsystem.

    The place for this should be in the clock drivers in the Kernel, since this is the first time the LCDC module is brought up and configured, the associated PLL setup is performed there (using drivers/clk/ti/dpll.c and drivers/clk/ti/divider.c). Let me try to figure out how to change the config once we have the updated values...

    I have tried different commands like "hexdump" with no success, access denied to /dev/mem.

    Try using the `devmem2` tool. Once you have the register values James should be able to help to let us know what needs to be updated for Spread Spectrum Clocking (SCC).

    Regards, Andreas

  • Thanks for your answer, sorry but I failed using devmem2, when I tried to install it I got the message "unable to locate package devmem2". Is there another way to know the parameters used for the PLL setup. I am a complete beginner regarding the beaglebone and debian. I know we use kernel 3.8 from github adding 2 patched source code "ti_am335x_tsc.c" and "BB-BONE-LCD7-01-00A3.dts". Is it possible to know which parameters are used by dpll.c and divider.c from the kernel source code?

    Regards

    Gilles

  • Hi Gilles,

    Andreas is out of office today. Please expect delayed response.