[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP : LFOSC usage in the processor

We are using AM6254 in our design.

We want to understand the use of these optional signals i.e. MCU_Ext_REFCLK0, EXT_REFCLK. Currently we have provided clock inputs on MCU_OSC pins(25MHz) and on the WKUP_LFOSC0(32.768KHz).We want to understand further if these MCU_Ext_REFCLK0, EXT_REFCLK pins can be excluded.

These are optional clock inputs. You can search the AM62x TRM for these names and it will show you all modules which can be clocked from these inputs. 

You will need to determine if a separate reference clock is required for these modules based on your specific system implementation.

Your system may be able to use internal clocking options for each of these modules. If so, external clock sources will not be required for these inputs.

AM623: How to enable Low-Frequency Oscillator with External Crystal?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1331335/am623-how-to-enable-low-frequency-oscillator-with-external-crystal/5068239

AM625: RTC(WKUP_LFOSC0) is low voltage
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1247605/am625-rtc-wkup_lfosc0-is-low-voltage

AM625: AM625: RTC(WKUP_LFOSC0) is low voltage (Continued)

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1273452/am625-am625-rtc-wkup_lfosc0-is-low-voltage-continued/4830820

(+) [FAQ] AM625: Crystal drive strength specifications - Processors forum - Processors - TI E2E support forums

Based on your follow-up for additional info please refer the inputs i received from the device expert.

The crystal power dissipation will depend on the crystal they select and the crystal circuit (including the load capacitance) they implement. Our oscillator has an AGC that monitors oscillation of the crystal circuit and adjusts its gain to maintain oscillation. Therefore, it doesn’t have fixed drive strength.
Even if we told them our max drive strength, the power dissipation in the crystal would still depend on the crystal they select and the crystal circuit (including the load capacitance) they implement.
The formula for calculating crystal power dissipation in the crystal: Pxtal = 0.5 ESR (2 π Fxtal CL Vxtal).
Our oscillator could drive a voltage that approaches the potential of oscillator power supply. This is not very likely to occur with most crystal implementations. As you can see in the formula, the crystal power dissipation is still dependent on the ESR of the crystal circuit even if you assume a worst case value of 1.8V for Vxtal. Using a worst case value of 1.8V for Vxtal is very unrealistic for a typical crystal implementation since Vxtal is more likely to be 1.0V than 1.8V.

Additional inputs 

I have a query on the WKUP_CLKOUT0 use case Many customer use the pin to source clock to RF or WiFi modules – 32.768K
WKUP_CLKOUT0 defaults to 25M clock output
I am telling customers to ensure the reset is released only after the WKUP_CLKOUT0 is set to 32K
Did you have any thoughts or concerns or recommendations on the customers use case.

You need to confirm what the RF or WiFi modulese will do if you source a 25MHz clock into the 32.768kHz input, even when held in reset.

I would hope it is able to ignore this clock in such a way that it doesn’t create a problem as long as you wait and take nSHUTD high after the correct source has been selected, but that may not be the case. I would ask the team that supports RF or WiFi modules if I were designing this system.

As an example the CC256x device requires the slow clock frequency to be 32.768 kHz ±250 ppm. I’m not sure our 32k output is able to meet this requirement.

I spent some time looking at the WKUP_CLKOUT0 sources and determined the internal clock named “DEVICE_CLKOUT_32K”, which I assume is the one the customer plans to select for WKUP_CLKOUT0, can be sourced from one of three possible clock sources. The three sources are HFOSC_CLKOUT_32K, CLK_32K_RC, and LFOSC0_CLKOUT. The only one of these three that will be accurate enough for the TI CC256x device is LFOSC0_CLK, which means they must connect a 32.768kHz crystal circuit to the AM62x low frequency oscillator. However, it appears they are not planning to install the 32.768kHz crystal circuit components. If so, they would need to use one of the other two sources.

HFOSC_CLKOUT_32K is a integer divider of the HFOSC reference frequency. The closest you can get to 32.768kHz is 32.89474kHz with a divider of 760, or 32.55208kHz with a divider of 768. Note: The frequency error would be 126.74Hz or 3868 PPM at 32.89474kHz, which is over 15x the limit of 250 PPM.

The CLK_32K_RC would be even worse than HFOSC_CLKOUT_32K.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1262394/am62a7-q1-use-of-wkup_lfosc0

Internally generated 32 kHz clock sources are not as accurate as WKUP_LFOSC0. The customer should use the clock tree tool function in the SYSCONFIG tool to understand which internal functions could benefit from a more accurate 32 kHz clock. They would need to decide if their use case requires any of these functions to be clocked from a more accurate 32.768 kHz source.

Note: the SYSCONFIG tool can be found under Design & Development / Software Development in the AM62Ax product folder on ti.com.

 AM62P-Q1: Clock Accuracy 

 RE: AM625: Regarding AM6254 

1) AM62x provides a several optional clock inputs, WKUP_LFOSC0, AUDIO_EXT_REFCLK[1:0], EXT_REFCLK1, and MCU_EXT_REFCLK0. You should search the device TRM for each clock input to understand which internal modules can be clocked form each of these optional clock inputs. Then you need to determine if your specific system implementation is able to use one of the internal clock references or requires a external clock.

2) The internal 32k clock is generated from a integer divider of HFOSC operating frequency, which only supports 24 MHz , 25 MHz, or 26 MHz. For example, If HFOSC = 25 MHz, the internal 32k clock will be (25000000/95)/8= 32,894.7368 Hz or (25000000/96)/8= 32,552.0833 Hz. You may need to use WKUP_LFOSC0 if your application requires the internal 32k clock to be exactly 32,768 Hz.

 RE: PROCESSOR-SDK-AM62X: Clock generation accuracy from SOC 

AM62x simply connects the output of the WKUP_LFOSC0 to the WKUP_CLKOUT0 output buffer and the oscillating frequency of WKUP_LFOSC0 is completely dependent on the external crystal circuit components or LVCMOS clock source selected by the system designer.

Could customer use WKUP_CLKOUT0 to provide 32.768kHz clock

Tthe AM62x device powers-up sourcing the 25MHz clock from MCU_OSC0 by default. This much faster clock rate may create a problem for the attached device even if it is held in reset while waiting for software to configure the WKUP_CLKOUT0 pin with a 32.768 kHz clock. If not, they would still need to enable WKUP_LFOSC0 and change the internal wkup_clkout multiplexer to select the WKUP_LFOSC0 output rather than the MCU_OSC0 output.
Note: This multiplexer is not a glitch free multiplexer, so they would need to hold the attached device in reset until everything is configured and the WKUP_CLKOUT0 pin is sourcing the correct 32.768 kHz clock.

The other concern is the accuracy of WKUP_CLOCK when when generation 32.768 and is explained above