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Hi,
Hello Eric Laroche
Thank you for the query.
Is resitor termination in mandatory for RGMII bus bteween AM6442 and PHY ethernet ?
This helps improve signal integrity. Providing series resistors is specific to design.
TI recommends providing series resistors for the TX signals near to the SoC. Start with 0R.
In evaluation board, there is no termination resistor
EVM do not represent actual system implementation.
so I suppose that there are intgrated resistor temination in SITARA pin, or edge control settings ?
The SoC does not provide these provisions.
Or maybe it is because the lenght of RGMII bus is very short ?
The required simulations have been performed on the board. As i said the EVM does not represent actual system implementation.
Do remember it is up to the board designer to implement the recommendations.
We have a hardware design guide and schematics design and review checklist that you could follow.
Refer below FAQ that lists all the key collaterals that could be referenced.
Regards,
Sreenivasa