AM623: efuse

Hello Hong,

I have a question: OTP stands for One-Time-Programmable Memory, suggesting it can only be programmed once. So, why, in the FS-HS state without Write-Protected (WP), can multiple write operations occur? For instance, repeatedly writing SMPK-H into efuse. Which type of efuse in the am62x is described in the link below?

https://www.pufsecurity.com/technology/otp/

There are three different types of OTP programming mechanisms that are commercially available.

Floating gate-based OTP stores charges in its floating gate. The trapped charges can be erased by exposure to ultraviolet light or radiation, which is an advantage in specific niche markets and mature process nodes.
eFuse OTP is based on the electro-migration effect in polysilicon or metal strips and programmed by electrically blowing a strip of metal or poly. EFuse is vulnerable to physical attacks due to visible differences between programmed and unprogrammed bits, which is dangerous when secret or sensitive data needs to be stored.
Anti-fuse OTP is a secure OTP introduced to counter the visibility issue present in EFuse OTP. The programming mechanism in Anti-fuse OTP is based on avalanche breakdown, shorting the gate and source of a transistor. These results remain hidden, with randomized rupture spots in the oxide layer. This programming mechanism provides good data retention performance and ensures secure data storage against physical attacks, such as SEM analysis. 

Regards,

Li

Hello Hong,

I learned from the link below that the SYSFW API can be used to read and write extended OTP efuse in HS-SE mode.

I would like to know if there are any sample programs in the U-Boot and kernel that use the SYSFW API to read and write extended OTP efuse.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1235859/faq-how-to-program-the-extended-otp-efuse-on-am6x-soc

If there are no corresponding sample programs, how can I use the SYSFW API to read and write extended OTP efuse? Is there any corresponding documentation available?

Regards,

Li

Hello Hong,

I find the definition of 'struct tisci_msg_get_clock_req' in the following link.

https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/clocks.html#tisci-msg-get-clock

However, in the am62x SDK version 08_06_00_42  U-Boot, the definition of 'ti_sci_msg_req_get_clock_state' is inconsistent with the documentation above.

The 'struct tisci_msg_get_clock_req' in the above documentation has an additional member variable called 'clk32' , but there is no definition of member variables in the U-Boot code，as shown below:

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/drivers/firmware/ti_sci.h?h=ti-u-boot-2021.01&id=2ee8efd6543648c6b8a14d93d52a6038854035c8

/**
 * struct ti_sci_msg_req_get_clock_state - Request for clock state
 * @hdr:	Generic Header
 * @dev_id:	Device identifier this request is for
 * @clk_id:	Clock identifier for the device for this request.
 *		Each device has it's own set of clock inputs. This indexes
 *		which clock input to get state of.
 *
 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
 * of the clock
 */
struct ti_sci_msg_req_get_clock_state {
	struct ti_sci_msg_hdr hdr;
	u32 dev_id;
	u8 clk_id;
} __packed;

In this situation, how can this problem be solved??

Regards,

Li

Hello Li,
Let me check, and get back to you.
Best,
-Hong