AM623: LPDDR4 RAM Tuning

Vinay, the DDR driver is in u-boot in drivers/ram/k3-ddrss.  The driver reads a DDR configuration file in arch/arm/dts to initialize the DDR controller and PHY registers, and then kicks off the hardware driven initialization and training.  There are multiple registers which contain training results, the details of which are not in the TRM.  Can i ask what you will do with the information?  I assume you are looking for some sort of training validation?

Regards,

James

Yes, we are looking for training validation. Currently we are seeing dram mtest failures and with ecc enabled, we have observed multi bit errors. So we need to make sure the lpddr initialization and training values are configured properly. Please let us know the steps to validate training values.

Vinay, are you seeing mtest failures when ECC is disabled?  First try with ECC disabled to ensure proper configuration.  Once that is stable, then you can try to see if the ECC errors go away.

Regards,

James

James, yes we are seeing mtest failures when ECC is disabled.  We have also re checked the configuration. We are looking for how the lpddr initialization values and training values are validated. 

Vinay, can you send a DDR register dump using JTAG and CCS?  I will be able to tell at least if the training is completing correctly.  Can you also send DDR datasheet and your configuration?

Regards,

James

James, Please find the Data sheet and Configuration file attached. I will share the DDR register dump soon. 8Gb_LPDDR4_NT6AN512M16AV-Jx.pdfPrometheus_am62x_A0_112323_LPDDR4_sysconfig.zip

Vinay, it doesn't look like you filled out the sysconfig tool correctly.  For example, for tCMDCKE, your datasheet shows min MAX(1.75ns, 3nCK).  However you changed tCMDCKE_ns to 3.75ns.  It should be

tCMDCKE_ns = 1.75ns

tCMDCKE_tCK = 3

And so on for the other parameters.  You should have to do any calculations, let the tool do that. Just plug in the values from the spreadsheet

Regards,

James

James,

 Thank you for confirming that tool will do any calculations required. We had done the initial sysconfig without any calculation, but then we faced the issue mentioned above and we were not sure of tool will take care of calculation, we changed to calculated values. Attached the initial sysconfig we used. Prometheus_am62x_No_Conversion.zip

Vinay, 

ok that sysconfig looks typical.  The tMRRI actually can stay at 3tCK (the tRCD component is already in the formula), but other changes are typical.  So is your design is still showing memtest failures with this configuration?  If so, can you send me a DDR register dump?  You can do this by connected via JTAG and running the following GEL script AM62 DDRSS Debug->Memory Debug->AM62_DDRSS_CTL_PI_PHY_RegDump()

Regards,

James

James,

 Happy new year 2024.

We connected JTAG to get the registry dump. We could not find the exact GEL Script you mentioned. Could you please let me know where to get the same.  We got  one GEL script at ccs_base folder with which it is giving following error in CCS:

AM62_DDRSS_CTL_PI_PHY_RegDump() cannot be evaluated.
identifier not found: AM62_DDRSS_CTL_BASE
   at (AM62_DDRSS_CTL_BASE+DDRSS_CTL_0__SFR_OFFS) [AM62x_DDRSS_RegDump.gel:48]
   at AM62_DDRSS_CTL_PI_PHY_RegDump()

Hi Vinay, i think you are running the correct one, but there are some other GELs which it depends on.  The best thing to do is to setup a new Target Configuration with AM62x_LP_SKEVM, and then connect to R5 to take the regdump.  If you are new to CCS, let me know and i can step you through it.

Regards,

James

Please provide the steps in CCS it will be helpful. 

Open CCS and choose View -> Target Configurations

Right click on User Defined and choose New Target Configuration

Give the file a name and click Finish

Choose the connection based on the JTAG pod you have

For Board or Device, choose AM62x_LP_SKEVM and then click Save

Connect the JTAG cable and power up your board to boot.

Right click on the Target Configuration file you made and Launch Selected Configuration

Connect to the R5 and run the GEL script with Scripts->AM62x DDRSS Memory debug->AM62x_DDRSS_CTL_PI_PHY_RegDump()

Regards,

James

Thank you James for the steps. Please find the attached Registery dubp for the 2 configurations we have. 1. Initial config as per data sheet without any conversion. 2. Config with conversion. 

A-Sample-Lpddr4_RegistryDump_Initial_24112023.txt

0456.A-Sample-Lpddr4_RegistryDump_latest_24012024.txt

Vinay, i don't see any training issues in either of these register dumps.  Training appears to be completing.  The only difference i see is the memory side DQ VREF is lower in the latest dump, but i don't know if the higher value on the original config is contributing to the errors.

So to confirm, you are seeing similar errors with both of these configurations?  Can you send me a log of the errors?  Do you know if these errors are reads or writes?

Regards,

James