TDA4VM: SGMII Configuration issue

Hi Ethan,

Thanks for creating the thread.

Can you confirm that the phy is enabled for autonegotiation?

Regards,
Tanmay

Hi Tanmay

Yes, the phy is enabled for autonegotiation

Hi Ethan,

I see some prints in the cpsw driver in the logs. Can you share the prints statement you have added in the driver.

Can you also see if you are calling the "cdns_torrent_phy_init()" and "cdns_torrent_phy_on()" function in "drivers/phy/cadence/phy-cadence-torrent.c"

Also, in your device tree in "serdes4_sgmii_link" node can you replace the "resets" property with just "resets = <&serdes_wiz4 1>;"

And in your wiz node, can you change the "assigned-clock-parents" from <&k3_clks 297 10> to <&k3_clks 297 13>.

Regards,
Tanmay

Hi Tanmay

I see some prints in the cpsw driver in the logs. Can you share the prints statement you have added in the driver.

--please see the attachment.

Can you also see if you are calling the "cdns_torrent_phy_init()" and "cdns_torrent_phy_on()" function in "drivers/phy/cadence/phy-cadence-torrent.c"

--I have added logs for these 2 functions. Please refer to the attachment for logs and modifications

Also, in your device tree in "serdes4_sgmii_link" node can you replace the "resets" property with just "resets = <&serdes_wiz4 1>;"

And in your wiz node, can you change the "assigned-clock-parents" from <&k3_clks 297 10> to <&k3_clks 297 13>.

--I already tried. It didn't work

COM21(2023-11-14 14_15_12).txt

--- D:\Programs\virtualBoxVms\shareFile\ti-processor-sdk-linux-j7-evm-08_06_01_02\board-support\linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56\drivers\base\power\domain.c	2023-05-02 23:40:21.000000000 +0800
+++ D:\Programs\virtualBoxVms\shareFile\domain.c	2023-10-05 08:53:56.000000000 +0800
@@ -2574,12 +2574,13 @@
 	struct of_phandle_args pd_args;
 	struct generic_pm_domain *pd;
 	int ret;
 
 	ret = of_parse_phandle_with_args(dev->of_node, "power-domains",
 				"#power-domain-cells", index, &pd_args);
+	dev_info(dev, "__genpd_dev_pm_attach11111111111111:%d\n",ret);
 	if (ret < 0)
 		return ret;
 
 	mutex_lock(&gpd_list_lock);
 	pd = genpd_get_from_provider(&pd_args);
 	of_node_put(pd_args.np);
@@ -2606,12 +2607,13 @@
 	dev->pm_domain->sync = genpd_dev_pm_sync;
 
 	if (power_on) {
 		genpd_lock(pd);
 		ret = genpd_power_on(pd, 0);
 		genpd_unlock(pd);
+		dev_info(dev, "__genpd_dev_pm_attach444444444444:%d\n",ret);
 	}
 
 	if (ret)
 		genpd_remove_device(pd, dev);
 
 	return ret ? -EPROBE_DEFER : 1;
@@ -2638,13 +2640,16 @@
 	/*
 	 * Devices with multiple PM domains must be attached separately, as we
 	 * can only attach one PM domain per device.
 	 */
 	if (of_count_phandle_with_args(dev->of_node, "power-domains",
 				       "#power-domain-cells") != 1)
+	{
+		dev_info(dev, "of_count_phandle_with_args222222222\n");
 		return 0;
+	}
 
 	return __genpd_dev_pm_attach(dev, dev, 0, true);
 }
 EXPORT_SYMBOL_GPL(genpd_dev_pm_attach);
 
 /**
@@ -2673,12 +2678,13 @@
 	if (!dev->of_node)
 		return NULL;
 
 	/* Verify that the index is within a valid range. */
 	num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
 						 "#power-domain-cells");
+		dev_info(dev, "genpd_dev_pm_attach_by_id33333333333:%d\n",num_domains);
 	if (index >= num_domains)
 		return NULL;
 
 	/* Allocate and register device on the genpd bus. */
 	virt_dev = kzalloc(sizeof(*virt_dev), GFP_KERNEL);
 	if (!virt_dev)

--- D:\Programs\virtualBoxVms\shareFile\1009bak\board-support\linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56\drivers\phy\cadence\phy-cadence-torrent.c	2023-10-09 18:59:13.000000000 +0800
+++ D:\Programs\virtualBoxVms\shareFile\phy-cadence-torrent.c	2023-11-14 14:09:29.000000000 +0800
@@ -1608,19 +1608,21 @@
 {
 	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
 	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
 	u32 read_val;
 	int ret;
 
+	dev_info(cdns_phy->dev, "cdns_torrent_phy_on, cdns_phy->nsubnodes:%d \n", cdns_phy->nsubnodes);
 	if (cdns_phy->nsubnodes == 1) {
 		/* Take the PHY lane group out of reset */
 		reset_control_deassert(inst->lnk_rst);
 
 		/* Take the PHY out of reset */
 		ret = reset_control_deassert(cdns_phy->phy_rst);
 		if (ret)
+			dev_err(cdns_phy->dev, "cdns_torrent_phy_on reset_control_deassert, ret:%d\n", ret);
 			return ret;
 	}
 
 	/*
 	 * Wait for cmn_ready assertion
 	 * PHY_PMA_CMN_CTRL1[0] == 1
@@ -2081,12 +2083,13 @@
 	struct cdns_torrent_vals *pcs_cmn_vals;
 	struct cdns_reg_pairs *reg_pairs;
 	struct regmap *regmap;
 	u32 num_regs;
 	int i, j;
 
+	dev_info(cdns_phy->dev, "cdns_torrent_phy_init, cdns_phy->nsubnodes:%d \n", cdns_phy->nsubnodes);
 	if (cdns_phy->nsubnodes > 1) {
 		if (phy_type == TYPE_DP)
 			return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
 		return 0;
 	}
 
@@ -2564,12 +2567,13 @@
 	struct device_node *child;
 	int ret, subnodes, node = 0, i;
 	u32 total_num_lanes = 0;
 	int already_configured;
 	u8 init_dp_regmap = 0;
 	u32 phy_type;
+	dev_info(dev, "\t[SIERRA] %s : cdns_torrent_phy_probe\n", __func__);
 
 	/* Get init data for this PHY */
 	data = of_device_get_match_data(dev);
 	if (!data)
 		return -EINVAL;
 

BR

Ljc

Hi Ethan,

Would it be possible to have a debug call early next week? I will get more clarity on your setup and thing will also go faster that way.

Regards,
Tanmay

Hi Tanmay

Thanks! Please tell me when you are free, I'll communicate with customers

Hi Tanmay

Ping the thread again to determine the latest progress

Hi Ethan,

Sorry for the delay.

Can you try with this serdes configuration : 

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 13>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
/*
			torrent_phy_dp: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>;
				cdns,phy-type = <PHY_TYPE_DP>;
				cdns,num-lanes = <4>;
				cdns,max-bit-rate = <5400>;
				#phy-cells = <0>;
			};
*/
			serdes4_sgmii_link: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>, <&serdes_wiz4  2>, <&serdes_wiz4 3>, <&serdes_wiz4 4>;
				cdns,phy-type = <PHY_TYPE_SGMII>;
				cdns,num-lanes = <4>;
				#phy-cells = <0>;
			};
		};
	};

Regards,
Tanmay