AM6442: How to apply the workaround of i2189

Greetings Hideaki,

I believe our S/W offerings already encompass this workaround, both our Processor SDK Linux and MCU+SDK should have drivers with this. I will have the other teams examine this ticket to give more specific information.

Sincerely,

Lucas

Hello Hideaki,

Thanks for your query.

We are looking into this, please expect responses within a day or two.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav, Lucas,

Thank you so much for following up this thread. OK, I'm waiting for your update. Since the customer needs your answer within this week, it would be very helpful if we can close this problem within a day or two.

Thanks and regards,
Hideaki

Hi Hideaki,

While looking through this, I found that the errata is i2189.

So yesterday and today first half I was searching the wrong number as in question you have mentioned the following.

Hideaki Matsumoto said:

Regarding the i2289 OSPI: Controller PHY Tuning Algorithm of AM64x/AM243x Errata Silicon Revision 1.0, 2.0, it seems that the following Workaround(s) must be implemented in order to use DQS of OSPI. Since it is difficult for them to create from scratch, they have a question and request below.

I am looking at this and will update in sometime.

Thanks,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Thank you for your reply. Yes, you're correct. It's i2189. Sorry, I wrote wrong number.

I'm expecting your update.

Thanks and regards,
Hideaki

Hello Hideaki,

Please expect responses by today(11/20/2023).

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Hideaki,

I am still looking into this and checking internally.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Hideaki,

I have checked with the development team. 

In the API OSPI_phyTuneDDR() in ospi_phy.c, the tuning is done according to the app note mentioned in the errata.

Could you please point this to the customer and recheck?

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Thank you for your reply. We've received the feedback from the customer.

They understood that the tuning is done in the API OSPI_phyTuneDDR().

Are not only the tuning but also all of the following workarounds 1 to 3 applied in this API ?

https://www.ti.com/lit/spract2). To sample data under some PVT conditions, it is necessary to increment the Read Delay field to shift the internal clock sampling window. This allows sampling of the data anywhere within the data eye. However, this has these side effects:

1. PHY Pipeline mode must be enabled for all read operations. Because PHY Pipeline mode must be disabled for writes, reads and writes must be handled separately.
2. Hardware polling of the busy bit is broken when the workaround is in place, so SW polling must be used instead. Writes must occur through DMA accesses, within page boundaries, to prevent interruption from either the host or the flash device. Software must poll the busy bit between page writes. Alternatively, writes can be performed in non-PHY mode with hardware polling enabled.
3. STIG reads must be padded with extra bytes, and the received data must be rightshifted.

Thanks and regards,
Hideaki

Hello Hideaki,

I have taken your question into my consideration.

I will check this and provide a response here in sometime.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Vaibhav,

Thank you for your reply. OK, I'm waiting for any update.

Thanks and regards,
Hideaki Matsumoto

Hello Hideaki,

Please expect responses by today.

Regards,

Vaibhav

ARM Based Processors | FAQ AM62x & AM62A | FAQ AM64x

Hi Hideaki,

Regarding your question on the workarounds, here are my answers:

1. PHY pipeline mode is enabled for reads given that DMA is enabled for reads. During the tuning mostly that's not the case, so we tune it with pipeline disabled. If the reads are done by CPU, then enabling the pipeline wasn't working for us. Whenever reads are done with DMA enabled, we enable the PHY pipeline. Hope that answered your question.
2. We use SW polling always, so I think need not worry about this point.
3. During reads with PHY enabled, I don't think there are STIG reads (at least not ones which requires precise data to be read). Currently the PHY is enabled just before the read, and is disabled once the read is complete. Even the RD CAPTURE DELAY is switched back after the read using PHY is done.

Hope that answers your question. Let me know if there are more queries.

Regards,
Anand Mahadevan SS

Hi Anand,

Thank you so much for your answers.

The custoer would like to double check as a conclusion.

As the workaround for i2189, they don't need any additional modification by themselves other than using API OSPI_phyTuneDDR() in the ospi_phy.c. Is this correct ?

Thanks and regards,
Hideaki 

Hi Hideaki,

Please expect responses in sometime.

Thanks,

Vaibhav