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TDA4AL-Q1: Some questions about CAN watermark

Part Number: TDA4AL-Q1

Hi,

I'm a little confused about the watermark Settings.

1. Is there more msg in the FIFO than watermark, so the system will keep triggering interrupts?

2. I want to read out all the MSGS in the FIFO, but I did not find a function for this, could you please inform me?

3. If a device sends 20 packets to me within 50ms, the frame interval may reach 200us, so in order to receive data without losing frames, what is the appropriate watermark for me?

Thanks

  • Hello,

    Thanks for raising another E2E as requested

    1. FIFO and Watermark: The watermark level determines when the receive buffer generates an interrupt.If the FIFO contains more messages than the watermark level, it will trigger interrupts until the buffer's message count falls below the watermark level. So, yes, if the number of messages exceeds the watermark, the system will continue to generate interrupts until the FIFO's message count drops below this threshold.
    2. Reading Out Messages from FIFO: Typically, you'd have to dequeue or read messages from the FIFO until it's empty. Can_mcanReadRxFIFO API will be doing that.
    3. Setting the Appropriate Watermark: To prevent frame loss and ensure timely reception of messages, you need to consider the incoming message rate and the processing capabilities of your system. If you anticipate 20 packets arriving within 50ms which averages to 400 packets per second, you would want a watermark that can handle this rate without overflow. Given the frame interval of 200us, you'd likely need a relatively high watermark level to prevent overflow.Determining the precise watermark level might involve testing and optimization based on your system's performance.

    Regards

    Tarun Mukesh

  • Hi,

    Thanks for your reply.

    I refer to the read method in "pdk_j721s2/packages/ti/csl/example/mcan/mcanEvmLoopback/mcan_evm_loopback_app_main_k3.c" and use the "MCAN_readMsgRam" function to read data from the FIFO, but how do I know how much data is still unread in the FIFO? And, how do you know if the data in the FIFO is empty?

  • Hello li liu,

    I believe we need to look into MCAN_RXF0S register for FOGI and FOFL bits so that we can get to know how much data is still unread or to know the fill level in the FIFO 0.

    If possible can please connect a debugger and watch these values every time interrupt gets generated.

    Regards

    Tarun Mukesh