TDA4VL-Q1: adjust codec frequency

Hi Quanfeng, 

Is this for QNX or Linux?

Thanks,
Sarabesh S

Hi Sarabesh,

This is for Linux.

Thanks

Regards

quanfeng

Hi Quanfeng,

The clock is set in the wave5_set_dev_clk function in wave5-helper.c. The #defines for the clock frequency and pixel rate are located in the wave5-helper.h file. I am still working on determining what values to set these at to arrive at a clock frequency of 275MHz per noted in the datasheet.

Hi Sarabesh,

I can't find the wave5_set_dev_clk function in wave5-helper.c of Linux SDK 8.6, could you please tell me the exact path about this function?

I found that the clock frequency of 275MHz cannot be divided by PLL5 (2400MHz). When I changed it as follows, the clock frequency of Codec changed to 300MHz instead of 275M. How to resolve it?

--- a/ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j721s2/clocks.c
+++ b/ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/pdk_j721s2_08_06_01_03/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j721s2/clocks.c
@@ -5240,7 +5240,7 @@ static const struct clk_data_div_reg clk_data_hsdiv1_16fft_main_5_hsdiv0 = {
 static const struct clk_data_div_reg clk_data_hsdiv1_16fft_main_5_hsdiv1 = {
        .data_div               = {
                .n              = 128,
-               .default_div    = 4,
+               .default_div    = 8,
        },
        .reg                    = 0x00680000UL + (0x1000UL * 5UL) + 0x80UL + (0x4UL * 1UL),
        .bit                    = 0,

Thanks

Regards

quanfeng

Hi Quanfeng, 

Quanfeng Fu said:

I can't find the wave5_set_dev_clk function in wave5-helper.c of Linux SDK 8.6, could you please tell me the exact path about this function?

This is a relatively new patch we added. Would you be able to update to the latest 9.1 SDK release? Then you will see the function I am referring to.

Thank you,
Sarabesh S

Hi Sarabesh,

Sarabesh Srinivasan said:

Would you be able to update to the latest 9.1 SDK release?

Due to project needs, I am sorry that I cannot update to the 9.1 SDK. 

Sarabesh Srinivasan said:

I am still working on determining what values to set these at to arrive at a clock frequency of 275MHz per noted in the datasheet.

Is there any progress on this issue?

Thanks

Regards

quanfeng

Hi Sarabesh,

Sarabesh Srinivasan said:

Yes, I looked further into this issue, and can confirm you are correct here that the clock division to get 275MHz is not supported and the closest frequency division would result in 300MHz. 

300MHz is greater than the maximum frequency. Does it affect the stability of the chip operation?

If yes, what is the recommended solution?

Thanks

Regards

quanfeng