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Hi experts.
we have a problem on the NAND FLASH.
we found the GPMC (AM62X datasheet):
Supports up to 4 independent chip-select regions of programmable size and programmable base addresses on 16MB, 32MB, 64MB, or 128MB boundary in a total address space of 1GB.
but now we use a nand with 2048MBytes 。the system can work .
why the system can work on the space of 2GB ,but the interface just has a total address space of 1GB ?
Hello Helen Han,
Thank you for the query.
The addressing schemes are different.
Please refer below for info related to nand flash.
https://user.eng.umd.edu/~blj/CS-590.26/micron-tn2919.pdf
Regards,
Sreenivasa
Hi, I want to know the max space address for GPMC interface. does it support for 16GB NAND ?
Hello Helen Han,
I want to know the max space address for GPMC interface. does it support for 16GB NAND ?
Could you please help us understand the use case.
Regards,
Sreenivasa
HI , we find GPMC in the AM62X datasheet. its main features supports in a total address space of 1GB. but now we have used a 2GB(2048Mbytes) nand flash . the linux system runs well .we want to know how it works? because the nand address 2GBytes exceeds the 1GB address space .
Hello Helen Han,
The 1GB (this is 128 MB) is memory mapped.
NAND memory is a block device and it's not directly addressable by the GPMC address pins. The data pins are used as address pins allowing the SoC to access larger NAND flash.
Please read below section of TRM.
12.4.3 General-Purpose Memory Controller (GPMC)
Regards,
Sreenivasa
Hello Zane Wei,
NAND memory is a block device and it's not directly addressable by the GPMC address pins.
Regards,
Sreenivasa