Hi,
We use SDK 8.6 and run it in MCU 1_ Many security features have been enabled on 0, and it has been found that there is a probability of only printing the first two logs on the Linux side during startup. Have you encountered this problem before? Where should we look for the problem?
Regards,
Guocai Yang
Hi,
I am searching for the current core MCU 1_ 0 the log was found to have failed during the PBIST self-test function of A72 core.
The following is the PBIST_runTest function we use. There are no additional error messages in the printed Log, and there are only three step errors in this function without any additional error messages.
/* This function runs the full PBIST test for a particular section.
* It includes the following steps (each step has many sub-steps specificied
* in more details within the function).
* For HW POST PBIST:
* Step 1: Configure interrupt handler
* Step 2: Check POST results (already run at startup)
*
* For SW-initiated PBIST:
* Step 1: Configure interrupt handler
* Step 2: Configure processor to correct state
* Step 3: Run PBIST test (includes checking the result)
* Step 4: Restore cores
* */
int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
{
int32_t testResult = 0;
SDL_ErrType_t status;
bool PBISTResult = true;
SDL_PBIST_testType testType;
uint32_t i = 0;
uint32_t moduleState = TISCI_MSG_VALUE_DEVICE_HW_STATE_OFF;
uint32_t resetState = 0U;
uint32_t contextLossState = 0U;
#if defined(PROFILE_PBIST_TIMING)
uint64_t startTime , testStartTime, testEndTime, endTime;
uint64_t prepTime, diffTime, restoreTime;
#endif
#if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)
if (test == PBIST_TEST_NEGATIVE)
{
UART_printf("\n Starting PBIST failure insertion test on %s, index %d...\n",
PBIST_TestHandleArray[instanceId].testName,
instanceId);
testType = SDL_PBIST_NEG_TEST;
}
else if (test == PBIST_TEST_POSITIVE)
{
UART_printf("\n Starting PBIST test on %s, index %d...\n",
PBIST_TestHandleArray[instanceId].testName,
instanceId);
testType = SDL_PBIST_TEST;
}
else
{
UART_printf("\n Starting PBIST Test Of ROM on %s, index %d...\n",
PBIST_TestHandleArray[instanceId].testName,
instanceId);
testType = SDL_PBIST_TEST_OF_ROM;
}
#else
if (test == 1u)
{
UART_printf("\n Starting PBIST failure insertion test on %s, index %d...\n",
PBIST_TestHandleArray[instanceId].testName,
instanceId);
testType = SDL_PBIST_NEG_TEST;
}
else
{
// UART_printf("\n Starting PBIST test on %s, index %d...\n",
// PBIST_TestHandleArray[instanceId].testName,
// instanceId);
testType = SDL_PBIST_TEST;
}
#endif
#if defined(PROFILE_PBIST_TIMING)
/* Get start time of test */
startTime = TimerP_getTimeInUsecs();
#endif
/* Step 1: (if HW Power-On Self Test, i.e. POST) Check POST results */
if ((testResult == 0) &&
(PBIST_TestHandleArray[instanceId].numPostPbistToCheck > 0))
{
if (test == 0u)
{
#ifdef DEBUG
UART_printf(" HW POST: Running test on HW POST, %d Instances \n",
PBIST_TestHandleArray[instanceId].numPostPbistToCheck);
#endif
SDL_PBIST_postResult result;
status = SDL_PBIST_getPOSTStatus(&result);
if (status != SDL_PASS)
{
testResult = -1;
UART_printf(" SDL_PBIST_getPOSTStatus failed: Status %d \n", status);
}
else
{
PBIST_printPostStatus(&result);
}
}
}
else
{
/* Step 2: (if SW-initiated PBIST) Configure processor to correct state */
/**--- Step 2a: Request Primary core ---*/
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if (PBIST_TestHandleArray[instanceId].tisciProcId != 0u)
{
#ifdef DEBUG
UART_printf(" Primary core: %s: Requesting processor \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
/* Request Primary core */
status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciProcId,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciProcId);
testResult = -1;
}
}
}
/**--- Step 2b: Request Secondary core ---*/
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecProcId != 0u))
{
#ifdef DEBUG
UART_printf(" Secondary core: %s: Requesting processor \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
/* Request secondary core */
status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciSecProcId,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciSecProcId);
testResult = -1;
}
}
}
#if defined (SOC_J784S4)
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThProcId != 0u))
{
#ifdef DEBUG
UART_printf(" Third core: %s: Requesting processor \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
/* Request third core */
status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciThProcId,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciThProcId);
testResult = -1;
}
}
}
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoProcId != 0u))
{
#ifdef DEBUG
UART_printf(" Fourth core: %s: Requesting processor \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
/* Request fourth core */
status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciFoProcId,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciFoProcId);
testResult = -1;
}
}
}
#endif
/**--- Step 2c: Put Primary core in local reset ---*/
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0u)
{
/* Set Local reset for Primary core */
#ifdef DEBUG
UART_printf(" %s: Primary core: Set module reset \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciDeviceId,
0x1, /* Local Reset asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_pmSetModuleRst...FAILED \n");
testResult = -1;
}
}
}
/**--- Step 2d: Put Secondary core in local reset ---*/
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0u))
{
/* Set Local reset for Secondary core */
#ifdef DEBUG
UART_printf(" %s: Secondary core: Set Module reset \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
0x1, /* Local Reset asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core: Sciclient_pmSetModuleRst...FAILED \n");
testResult = -1;
}
}
}
#if defined(SOC_J784S4)
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0u))
{
/* Set Local reset for Third core */
#ifdef DEBUG
UART_printf(" %s: Third core: Set Module reset \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
0x1, /* Local Reset asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core: Sciclient_pmSetModuleRst...FAILED \n");
testResult = -1;
}
}
}
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0u))
{
/* Set Local reset for Fourth core */
#ifdef DEBUG
UART_printf(" %s: Fourth core: Set Module reset \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
0x1, /* Local Reset asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core: Sciclient_pmSetModuleRst...FAILED \n");
testResult = -1;
}
}
}
#endif
#ifdef POWERUP_CORES_BEFORE_TEST
/**--- Step 2e: Perform any additional power sequencing, if needed ---*/
/* Custom core power restore sequence - needed to allow core to be powered
* up later by Secondary Bootloader (SBL) */
if ((testResult == 0) &&
(PBIST_TestHandleArray[instanceId].coreCustPwrSeqNeeded) &&
(PBIST_TestHandleArray[instanceId].tisciProcId != 0u))
{
status = customPrepareForPowerUpSequence(PBIST_TestHandleArray[instanceId].tisciProcId);
if (status != CSL_PASS)
{
UART_printf(" Custom core power restore sequence, ProcId 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciProcId);
testResult = -1;
}
}
/**--- Step 2f: Power up of Auxilliary modules needed to run test */
if (testResult == 0)
{
/* Power all modules required for test */
for ( i = 0; i < PBIST_TestHandleArray[instanceId].numAuxDevices; i++)
{
#ifdef DEBUG
UART_printf(" Powering on Device number %d Device Id %x\n",
i, PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i],
TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]);
testResult = -1;
break;
}
}
}
/**--- Step 2g: Power up Primary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0U))
{
/* power on Primary core*/
#ifdef DEBUG
UART_printf(" Primary core: Powering on %s \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciDeviceId);
testResult = -1;
}
}
/**--- Step 2h: Power up Secondary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
{
/* power on Secondary core*/
#ifdef DEBUG
UART_printf(" Secondary core: Powering on %s \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core: Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciSecDeviceId);
testResult = -1;
return testResult;
}
}
}
#if defined(SOC_J784S4)
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
{
/* power on Third core*/
#ifdef DEBUG
UART_printf(" Third core: Powering on %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core: Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciThDeviceId);
testResult = -1;
return testResult;
}
}
}
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
{
/* power on Fourth core*/
#ifdef DEBUG
UART_printf(" Fourth core: Powering on %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core: Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciFoDeviceId);
testResult = -1;
return testResult;
}
}
}
#endif
/**--- Step 2i: Double check the Power up of Auxilliary modules needed to run test
* and wait until they are powered up */
if (testResult == 0)
{
/* Wait for all modules required for test to be powered up */
for ( i = 0; i < PBIST_TestHandleArray[instanceId].numAuxDevices; i++)
{
#ifdef DEBUG
UART_printf(" Double checking Powering on Device number %d Device Id %x\n",
i, PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]);
#endif
do
{
status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i],
&moduleState,
&resetState,
&contextLossState,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Sciclient_pmGetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]);
testResult = -1;
break;
}
} while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON);
}
}
/**--- Step 2j: Double check the Power up of Primary core and wait until it is
* powered up */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0U))
{
/* Double check power on Primary core*/
#ifdef DEBUG
UART_printf(" Primary core: Double checking Powering on %s \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
do
{
status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId,
&moduleState,
&resetState,
&contextLossState,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_pmGetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciDeviceId);
testResult = -1;
break;
}
} while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON);
}
/**--- Step 2k: Double check the Power up of Primary core and wait until it is
* powered up */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
{
/* Double check power on Secondary core*/
#ifdef DEBUG
UART_printf(" Secondary core: Double checking Powering on %s \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
do
{
status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
&moduleState,
&resetState,
&contextLossState,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core: Sciclient_pmGetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciSecDeviceId);
testResult = -1;
break;
}
} while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON);
}
}
#if defined(SOC_J784S4)
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
{
/* Double check power on Third core*/
#ifdef DEBUG
UART_printf(
" Third core: Double checking Powering on %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
do
{
status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
&moduleState,
&resetState,
&contextLossState,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core: Sciclient_pmGetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciThDeviceId);
testResult = -1;
break;
}
} while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON);
}
}
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
{
/* Double check power on Fourth core*/
#ifdef DEBUG
UART_printf(
" Fourth core: Double checking Powering on %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
do
{
status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
&moduleState,
&resetState,
&contextLossState,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core: Sciclient_pmGetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciFoDeviceId);
testResult = -1;
break;
}
} while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON);
}
}
#endif
#endif /* #ifdef POWERUP_CORES_BEFORE_TEST */
/**--- Step 2l: Power up PBIST */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId != 0u))
{
#ifdef DEBUG
UART_printf(" Powering on PBIST %d \n",
PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" PBIST Sciclient_pmSetModuleState 0x%x ...FAILED: retValue %d\n",
PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId, status);
testResult = -1;
}
}
/**--- Step 2m: Execute Auxialliary init function for any final core-internal register
* setup needed for the PBIST test */
if (testResult == 0)
{
if (PBIST_TestHandleArray[instanceId].auxInitRestoreFunction != 0)
{
status = PBIST_TestHandleArray[instanceId].auxInitRestoreFunction(TRUE);
if (status != CSL_PASS)
{
testResult = -1;
}
}
}
#if defined(PROFILE_PBIST_TIMING)
/* Get start time for PBIST test */
testStartTime = TimerP_getTimeInUsecs();
#endif
/**-- Step 3: Run PBIST test. --*/
status = SDL_PBIST_selfTest((SDL_PBIST_inst)PBIST_TestHandleArray[instanceId].pbistInst, testType, NULL, &PBISTResult);
if ((status != SDL_PASS) || (PBISTResult == false))
{
testResult = -1;
}
#if defined(PROFILE_PBIST_TIMING)
/* Record test end time */
testEndTime = TimerP_getTimeInUsecs();
#endif
/**-- Step 4: Restore cores --*/
/**--- Step 4a: Execute Auxilliary restore function to restore core-internal
* registers to original state */
if (testResult == 0)
{
if (PBIST_TestHandleArray[instanceId].auxInitRestoreFunction != 0)
{
status = PBIST_TestHandleArray[instanceId].auxInitRestoreFunction(FALSE);
if (status != CSL_PASS)
{
testResult = -1;
}
}
}
/**--- Step 4b: Power off PBIST */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId != 0u))
{
#ifdef DEBUG
UART_printf(" Powering off PBIST %d \n",
PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" PBIST Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId);
testResult = -1;
}
}
#ifdef POWERUP_CORES_BEFORE_TEST
#if defined(SOC_J784S4)
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
{
/* power off Fourth core*/
#ifdef DEBUG
UART_printf(" Fourth core: Powering off %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciFoDeviceId);
testResult = -1;
return testResult;
}
}
}
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
{
/* power off Third core*/
#ifdef DEBUG
UART_printf(" Third core: Powering off %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciThDeviceId);
testResult = -1;
return testResult;
}
}
}
#endif
/**--- Step 4c: Power off Secondary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U))
{
if (PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
{
/* power off Secondary core*/
#ifdef DEBUG
UART_printf(" Secondary core: Powering off %s \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciSecDeviceId);
testResult = -1;
return testResult;
}
}
}
/**--- Step 4d: Perform any custom/core-specific power down sequence */
if ((testResult == 0) &&
(PBIST_TestHandleArray[instanceId].coreCustPwrSeqNeeded) &&
(PBIST_TestHandleArray[instanceId].tisciProcId != 0u))
{
status = customPowerDownSequence(PBIST_TestHandleArray[instanceId].tisciProcId);
if (status != CSL_PASS)
{
UART_printf(" Custom core power down sequence, ProcId 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciProcId);
testResult = -1;
}
}
/**--- Step 4e: Power off Primary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciProcId != 0u)
&& (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
/* power off Primary core*/
#ifdef DEBUG
UART_printf(" Primary core: Powering off %s \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciDeviceId);
testResult = -1;
}
}
#ifndef SOC_J784S4
/**--- Step 4f: Power off of Auxilliary modules needed to run test */
if (testResult == 0)
{
/* Power all modules required for test */
for ( i = 0; i < PBIST_TestHandleArray[instanceId].numAuxDevices; i++)
{
#ifdef DEBUG
UART_printf(" Powering off Device number %d Device Id %x\n",
i, PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i],
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]);
testResult = -1;
break;
}
}
}
#endif
/**--- Step 4g: Perform any custom/core-specific power restore sequence needed to
* allow core to be powered up properly later */
if ((testResult == 0) &&
(PBIST_TestHandleArray[instanceId].coreCustPwrSeqNeeded) &&
(PBIST_TestHandleArray[instanceId].tisciProcId != 0u))
{
status = customPrepareForPowerUpSequence(PBIST_TestHandleArray[instanceId].tisciProcId);
if (status != CSL_PASS)
{
UART_printf(" Custom core power restore sequence, ProcId 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciProcId);
testResult = -1;
}
}
/**--- Step 4h: Take Primary core out of local reset */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0U))
{
#ifdef DEBUG
UART_printf(" Primary core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciDeviceId);
testResult = -1;
}
}
/**--- Step 4i: Take Secondary core out of local reset */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U))
{
#ifdef DEBUG
UART_printf(" Secondary core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecProcId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciSecDeviceId);
testResult = -1;
}
}
#if defined(SOC_J784S4)
/* Take Third core out of local reset */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U))
{
#ifdef DEBUG
UART_printf(" Third core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThProcId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciThDeviceId);
testResult = -1;
}
}
/* Take Fourth core out of local reset */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U))
{
#ifdef DEBUG
UART_printf(" Third core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoProcId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciFoDeviceId);
testResult = -1;
}
}
#endif
#endif /* #ifdef POWERUP_CORES_BEFORE_TEST */
/* Ensure that cores have been turned off to prepare for booting of the cores */
/**--- Step 4j: Power off Primary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0u)
{
/* Set Software Reset Disable State for Primary core */
#ifdef DEBUG
UART_printf(" %s: Primary core: Put in Software Reset Disable \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_pmSetModuleState...FAILED \n");
testResult = -1;
}
}
}
/**--- Step 4k: Power off Secondary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0u))
{
/* Set Software Reset Disable State for Secondary core */
#ifdef DEBUG
UART_printf(" %s: Secondary Core Put in Software Reset Disable \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core Sciclient_pmSetModuleState...FAILED \n");
testResult = -1;
}
}
}
#if defined(SOC_J784S4)
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0u))
{
/* Set Software Reset Disable State for Third core */
#ifdef DEBUG
UART_printf(" %s: Third Core Put in Software Reset Disable \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core Sciclient_pmSetModuleState...FAILED \n");
testResult = -1;
}
}
}
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0u))
{
/* Set Software Reset Disable State for Fourth core */
#ifdef DEBUG
UART_printf(" %s: Fourth Core Put in Software Reset Disable \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core Sciclient_pmSetModuleState...FAILED \n");
testResult = -1;
}
}
}
#endif
/**--- Step 4m: Release Primary core */
if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciProcId != 0u)
&& (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
/* release processor Primary core */
#ifdef DEBUG
UART_printf(" Primary core: Releasing %s \n",
PBIST_TestHandleArray[instanceId].coreName);
#endif
status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciProcId,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Primary core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciProcId);
testResult = -1;
}
}
/**--- Step 4n: Release Secondary core */
if (testResult == 0)
{
if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciSecProcId != 0u)
&& (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
/* release processor Secondary core */
#ifdef DEBUG
UART_printf(" Secondary core: Releasing %s \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciSecProcId,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
UART_printf(" Secondary core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciSecProcId);
testResult = -1;
}
}
}
#if defined(SOC_J784S4)
if (testResult == 0)
{
if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciThProcId != 0u)
&& (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
/* release processor Third core */
#ifdef DEBUG
UART_printf(" Third core: Releasing %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciThProcId,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Third core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciThProcId);
testResult = -1;
}
}
}
if (testResult == 0)
{
if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded)
&& (PBIST_TestHandleArray[instanceId].tisciFoProcId != 0u)
&& (PBIST_TestHandleArray[instanceId].procRstNeeded))
{
/* release processor Fourth core */
#ifdef DEBUG
UART_printf(" Fourth core: Releasing %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciFoProcId,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
{
UART_printf(" Fourth core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n",
PBIST_TestHandleArray[instanceId].tisciFoProcId);
testResult = -1;
}
}
}
#endif
#if defined(PROFILE_PBIST_TIMING)
/* Record end time */
endTime = TimerP_getTimeInUsecs();
prepTime = testStartTime - startTime;
diffTime = testEndTime - testStartTime;
restoreTime = endTime - testEndTime;
UART_printf(" Delta Cores prep time in micro secs %d \n",
(uint32_t)prepTime);
UART_printf(" Delta PBIST execution time in micro secs %d \n",
(uint32_t)diffTime);
UART_printf(" Delta Cores restore time in micro secs %d \n",
(uint32_t)restoreTime);
UART_printf(" PBIST complete %s, test index %d\n",
PBIST_TestHandleArray[instanceId].testName,
instanceId);
#endif
}
return (testResult);
}
Regards,
Guocai Yang
Hi,
I confirmed the error return location by setting the error return value as shown in the following figure:
Regards,
Guocai Yang
Hi,
In follow function:
At the end, it is set to -1 at the position shown in the following figure:
Regards,
Guocai Yang
Hi,
I added the modifications in the document but still failed, and the sentence in the above modification should not have been added because it only introduced the path rather than copying the file:
-SRCS_COMMON += bist.c lbist_utils.c pbist_utils.c lbist_defs.c pbist_defs.c bist_core_defs.c sdl_lbist.c sdl_pbist.c sdl_ip_lbist.c sdl_ip_pbist.c sdl_soc_lbist.c sdl_soc_pbist.c sdl_osal.c power_seq.c armv8_power_utils.c
+SRCS_COMMON += bist.c lbist_utils.c pbist_utils.c lbist_defs.c pbist_defs.c bist_core_defs.c sdl_lbist.c sdl_pbist.c sdl_ip_lbist.c sdl_ip_pbist.c sdl_soc_lbist.c sdl_soc_pbist.c sdl_osal.c power_seq.c armv8_power_utils.c osal_interface.c
Regards,
Guocai Yang
Hi,
I have done this function in FS_MCU_initZero(), and bist function run in bist_TaskFxn(), so I said have done SDL_TEST_osalInit before bist.
Regards,
Guocai Yang
Hi,
I'm sorry for the late reply. As shown in the picture I sent earlier, I'm sure it's because the variables pInfo->doneFlag were not set and not completed, the issue I identified is as shown in the following picture:
Regards,
Guocai Yang
HI,
I use the bist_examples of SDL library on SDK8.6 were tested, as shown in the following figure:
Regards,
Guocai Yang
Hi,
I have gone through all the modifications you provided before using the BIST example, and I also added this part to my own code. However, I found that it got stuck on C7X and did not continue to execute downwards.
Regards,
Guocai Yang
Hi,
Please refer to this snippet to to stitch multiple .rprc images into a multicore image.
NOTE:
1. In the above combined image command, Make sure you are writing the correct core number. It can found at (..\packages\ti\boot\sbl\soc\k3\sbl_slave_core_boot.h)
2. Provide path before each file, if and only if unable to execute the combined image step.
The .rprc file of the boot app (can_boot_app_mcu_rtos_mcu1_0_release.rprc) will be loaded on to the mcu1_0 core and the sciclient_clear_clec_secure_claim_c7x_1_release.rprc present in (PDK_INSTALL_PATH)/ti/drv/sciclient/tools/clearClecSecureClaim/ must be loaded on the C7x core.
Once you have generated the mulicore image, load it as the appimage.
Regards,
Josiitaa
