AM625: GPMC0_DATA Memory map is different.

Hi Zane,

I am routing your query to our GPMC hardware expert for comments.

Hello Zane, 

Please confirm the TRM revision you are using.

Please check the latest TRM on TI.com.

Regards,

Sreenivasa

Hello Zane, 

0x50000000 is the correct address for GPMC0_DATA

We have an FAQ that provides links to key collaterals including the TRM 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1183910/faq-am625-custom-board-hardware-design-collaterals-to-get-started

Regards,

Sreenivasa

Hi Sreenivasa,

Can you help me confirm if the following understanding is correct?
GPMC IP actually supports 1GB memory mapping (AM65 SOC memory mapping 1GB address space), but the memory mapping of GPMC on AM62 only allocates 128MB. If 4 chip selects are used, each chip select has a 32MB memory map to store data.

But what is the maximum external memory capacity that each chip select can support?

Best Regards,

Zane

Hello Zane, 

Thank you.

Zane Wei said:

GPMC IP actually supports 1GB memory mapping (AM65 SOC memory mapping 1GB address space), but the memory mapping of GPMC on AM62 only allocates 128MB. If 4 chip selects are used, each chip select has a 32MB memory map to store data.

But what is the maximum external memory capacity that each chip select can support?

Your understanding is correct. 

I do not believe there is a max size per CS specified (from hardware side)

If you are operating in synchronous mode we do not recommend using multiple CS chip select due to the challenges related to signal integrity and the effect on the performance.

Regards,

Sreenivasa

Since there is no activity for more than 6 months, will close the ticket. Please submit a new ticket if there is still issues.

Br, Tommy