Other Parts Discussed in Thread: J784S4XEVM, TPS2663
Our customer wants to power-down AM69x by turning-off the system power, i.e. dropping the supply voltage to the VCCA instead of orderly shutdown on PMIC (TPS6594133A). So the recommended power-down sequencing for AM69 may not be met.
As discussed in the thread below, it is very difficult to meet the recommended power-down sequencing by turning-off the system power.
TPS6594-Q1: Shutdown TPS6594133A when system power is turned off
The recommended power-down sequence in the AM69 data sheet specifies the delay times between each power supply ramp-down. In the case of "Isolated MCU and Main Domains Power-Down Sequencing", the delay times are specified as below.
• T0 – MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)
• T1 – Main DDR, SRAM Core, and SRAM CPU power domains start ramp-down. (0.5 ms)
• T2 – All core voltages start supply ramp-down. (2.5 ms)
• T3 – All 1.8V voltages start supply ramp-down. (3.0 ms)
• T4 – All 3.3V voltages start supply ramp-down. (3.5 ms)
AM69x Processors, Silicon Revision 1.0 datasheet (Rev. B)
6.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
Is it required to meet the delay times for power-down sequencing?
Can it be tolerated that all power supplies ramp-down at once (almost simultaneously) by turning-off the system power?
Best regards,
Daisuke
