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Original question:

[FAQ] J721S2XSOMXEVM: How to change DDR frequency for J721E EVM, J721S2 EVM, and J784S4 EVM?

J784S4XEVM: How to change DDR frequency for J784S4 EVM？

Jian Huang
Prodigy 120 points
Part Number: J784S4XEVM

Hello TI，

I changed the DDR frequency to 1866MHz according to the method in the link below, but the system cannot start. Can you help me find out the reason?

[FAQ] J721S2XSOMXEVM: How to change DDR frequency for J721E EVM, J721S2 EVM, and J784S4 EVM? - Processors forum - Processors - TI E2E support forums

SDK version ：09.00.01.03 

Boot log：

U-Boot SPL 2023.04-dirty (Jan 12 2024 - 14:35:26 +0800)
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
SPL initial stack usage: 13424 bytes
Trying to boot from MMC2
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE: BL31: v2.9(release):v2.9.0-dirty
NOTICE: BL31: Built : 14:12:59, May 22 2023
I/TC:
I/TC: OP-TEE version: 3.20.0 (gcc version 11.3.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

  • 0
    TI__Mastermind 41343 points

    Hi Jian,

    DDR can be a little tricky. Could you share what numbers you put for the highlighted portion?

    Additionally, could you see if you can try setting a different frequency such as 3200MT/s (1600 memory frequency) and see if you see similar behaviors? I have found from personal experience the certain frequencies have trouble initializing.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Prodigy 120 points

    Hi Takuma,

    Thank you for your reply!

    The picture below is the DRAM Timing setting at 1866MHz.

     I lowered the frequency to 1600MHz and it boot ok.

    We checked the PCB design and found no problems for the time being.

    Are there other recommend settings that can improve DDR performance, such as ODT?

    Regards,,

    HJ.

  • 0 in reply to Jian Huang
    TI__Mastermind 41343 points

    Hi HJ.

    Let me run this question by our DDR expert to see if he has recommendations. Please expect a day of delay in response.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Prodigy 120 points

    Hi Takuma,

    Is there any updated from DDR expert?

    Regards,

    HJ.

  • 0 in reply to Jian Huang
    TI__Mastermind 35310 points

    Hi ,

    I am able to reproduce the issue on the TI EVM at 3733 data rate, and it does not appear that the k3-clock driver is setting the SOC PLL to the correct frequency when targeting 3733 data rate.

    This issue occurs when the driver first sets the PLL to the DDR boot frequency (F0), then tries to configure for 3733 data rate. You can work-around this by first initializing the PLL to the target data rate (add line shown below) prior to setting the PLL to the boot frequency. 

    Can you please add the line shown below to the DDR driver and see if this allows the boot process to get further?

    https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/drivers/ram/k3-ddrss/k3-ddrss.c?h=09.00.00.007#n277 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 120 points

    Kevin,

    Thank you very much for your analysis and suggestions!

    We added the line of code you mentioned, and then it can start normally when the DDR rate is 3733.

    When we raised the DDR rate to 4000 or 4266, other problems occurred.

    Can you help analyze them?

    log（@4266 or 4000）：

    U-Boot SPL 2023.04-dirty (Jan 31 2024 - 10:14:39 +0800)
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed -121
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
    Timeout during frequency handshake
    ### ERROR ### Please RESET the board ###

    Regards,

    HJ.

  • 0 in reply to Jian Huang
    TI__Mastermind 35310 points

    Hi,

    Can you clarify if these issues are observed with the EVM at 4266 data rate, or your custom board?

    If occurring with the EVM, are you using the default DDR register configuration file provided in the SDK, or one that you generated by the DDR register configuration tool?

    Do the issues only occur with the software driver work-around described above, or occur even if using the pre-built tiboot3.bin binary provided by TI (files in link below)?

    https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-lOshtRwR8P/09.00.01.03/boot-adas-j784s4-evm.tar.gz 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 120 points

    Hi Kevin,

    The problem is on our custom board.

    It's ok on EVM.

    We checked the PCB design,

    1. We have done back-drilling on both the data and dqs signals, but not on the address and control signals.

    2. Pin delay is considered on custom PCB layout, but EVM does not seem to consider this.

    Not sure whether these two problems affect the performance of DDR.

    If so, is it possible to optimize it by adjusting the configuration (such as OTD)?

    PCB stackup：16layers

    Regards,

    HJ.