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AM69: SGMII reference clocks

Daisuke Maeda
Guru 20325 points
Part Number: AM69
Other Parts Discussed in Thread: TDA4VH

Our customer wants to know the tested combinations of interfaces and reference clocks supported by SerDes.

I already got the answer for PCIe.

e2e.ti.com/.../am69-pcie-reference-clocks

SerDes supports interfaces and reference clock frequencies listed below (Table 12-195) except Hyperlink.

The SerDes supports internal reference clock sources listed below (Table 12-203).

J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. C)
Table 12-195. SerDes Supported Standards
Table 12-203. SerDes Internal Reference Clock Selection

Can the MAIN_PLL2_HSDIV4_CLKOUT be used at 100 MHz as an internal reference clock source for SGMII?

Can the SERDESn_REFCLK_x be used at 100 MHz as an external reference clock input for SGMII?

Best regards,

Daisuke

  • 0
    TI__Guru 56263 points

    Hi Daisuke-san,

    I let our SGMII expert know about this thread. Please expect a response in 1~2 business days.

    Regards,

    Takuma

  • +1 in reply to Takuma Fujiwara
    TI__Mastermind 41430 points

    Hi Daisuke-san,

    Daisuke Maeda said:
    Can the MAIN_PLL2_HSDIV4_CLKOUT be used at 100 MHz as an internal reference clock source for SGMII?

    Yes, this can be done. Infact, by default the MAIN_PLL2_HSDIV4_CLKOUT at 100MHz is set as the reference clock for serdes in TDA4VH EVM and used for QSGMII. You can also use the same for 1G SGMII as well.

    Daisuke Maeda said:
    Can the SERDESn_REFCLK_x be used at 100 MHz as an external reference clock input for SGMII?

    Yes this is possible. Similar to how you would configure serdes for using PCIe with an 100MHz external ref clock, similar configuration with only the required lane configured as SGMII should be sufficient for using external reference clock.

    Regards,
    Tanmay