AM69: PCIe reference clocks

Hi Daisuke-san,

In terms of reference clock for SERDES/PCIe, there is an option either take in clock from an external clock generator or the output internal clock from SoC.

I think the most useful documentation to look at would be the PROC141E4(001)_SCH.pdf schematic file of J784S4 EVM which can be downloaded within the "Deisgn files" section of the EVM purchasing page: https://www.ti.com/tool/J784S4XEVM.

On the J784S4 EVM the x4LANE PCIe0 Interface takes clock from an external clock generator and schematic looks like the following (DNI=Do Not Install):

On the same EVM board, the x2LANE PCIe1 Interface(J17) uses the clock generated from SoC and schematic looks like the following:

When internal clock is used, then MAIN_PLL2_HSDIV4_CLKOUT will need to be selected and ACSPCIE enabled. An example of what that would look like in software would be this patch for Linux: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/8787.enable_5F00_internal_5F00_ref_5F00_clock_5F00_out_5F00_pcie1_5F00_j784s4.patch

Let me know if this answers your questions, and if not, please let me know which area needs more clarification.

Regards,

Takuma

Hi Takuma-san,

Thank you for your reply.

Daisuke Maeda said:

Q1) Is SERDESn_REFCLK_x an input/output or input only?

In datasheet:
Each PCIe subsystem has a differential reference clock output (PCIE_REFCLKn_N_OUT, PCIE_REFCLKn_P_OUT).
Each SERDES module has a differential reference clock input/output (SERDESn_REFCLK_N, SERDESn_REFCLK_P).

AM69x Processors, Silicon Revision 1.0 datasheet (Rev. A)
Table 6-88. PCIE Signal Descriptions
Table 6-89. SERDES0 Signal Descriptions
Table 6-90. SERDES1 Signal Descriptions
Table 6-91. SERDES2 Signal Descriptions
Table 6-92. SERDES4 Signal Descriptions

In TRM:
Each SERDES module has a differential reference clock output (PCIE_REFCLK_P_OUT, PCIE_REFCLK_N_OUT) and a differential reference clock input (SERDES_REFCLK_P, SERDES_REFCLK_N).

J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. C)
Figure 12-126. SerDes Environment
Table 12-204. SerDes Input/Output Description

Is SERDESn_REFCLK_x an input only? Are the descriptions in the datasheet incorrect?

Daisuke Maeda said:

Q2) Can SERDESn_REFCLK_x be used as a reference clock for SerDes?

In TRM, it seems that the internal reference clock for SerDes can only be selected from internal clock sources.

J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. C)
Table 12-203. SerDes Internal Reference Clock Selection

If SERDESn_REFCLK_x is used as a reference clock for SerDes, how are the registers configured?

No registers details are found in the TRM. Where can we find the registers details?

No Clock Tree Tool for J784S4 devices is found in the link below. Is there the Clock Tree Tool for J784S4 devices?

www.ti.com/.../CLOCKTREETOOL

Best regards,

Daisuke

Hi Daisuke-san,

SERDESn_REFCLK_x can definitely take in an input, but I will need to check if it can support outputting a REFCLK. For PCIe in our SDK, outputting the REFCLK comes not from SERDESn_REFCLK_x, but instead, it comes from PCIE_REFCLKx_OUT if wanting to use the internal refclk instead of providing an external refclk.

Register details should be in the excel sheet included in the zip file of the TRM.

For clock information, I would recommend this documentation: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html#. Unfortunately, we do not have support fot J784S4 for the clocktreetool.

Regards,

Takuma

Hi Takuma-san,

Thank you for your reply.

Takuma Fujiwara said:

SERDESn_REFCLK_x can definitely take in an input, but I will need to check if it can support outputting a REFCLK. For PCIe in our SDK, outputting the REFCLK comes not from SERDESn_REFCLK_x, but instead, it comes from PCIE_REFCLKx_OUT if wanting to use the internal refclk instead of providing an external refclk.

Please check if SERDESn_REFCLK_x can support reference clock output. If the data sheet is incorrect, please correct it.

Takuma Fujiwara said:

Register details should be in the excel sheet included in the zip file of the TRM.

Sorry. I completely overlooked the excel sheet.

Takuma Fujiwara said:

For clock information, I would recommend this documentation: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html#. Unfortunately, we do not have support fot J784S4 for the clocktreetool.

The Clock Tree Tool is very useful for understanding how the clocks are interconnected throughout the device.

Are there any plans for the Clock Tree Tool to be released for the J784S4?

Best regards,

Daisuke

Hi Daisuke-san,

Currently, I am out of office, so I would not be able to dig deeply into these questions. Please expect 2 weeks of delay in response.

Regards,

Takuma

Hi Takuma-san,

Thank you for your reply.

I have some additional questions.

The clock sources listed below are selectable for the reference clock, but I do not know what some of the clock sources (highlighted below) mean.

What do these clocks mean?

SERDESx_REF_DER_OUT_CLK
SERDESx_REF_OUT_CLK
HFOSC0_CLKOUT
HFOSC1_CLKOUT

Does HFOSC0_CLKOUT mean WKUP_HFOSC0_CLKOUT?

The SerDes reference clocks can be selected externally (clock input) or internally.

How to switch between external and internal for the SerDes reference clocks?

The patch for Linux you showed only configures the clock outputs.

Takuma Fujiwara said:

Currently, I am out of office, so I would not be able to dig deeply into these questions. Please expect 2 weeks of delay in response.

I understand the delay in response due to the holiday season, but I expect your answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Takuma-san,

Thank you for your support. Our customer is waiting for your reply.

Sorry for the many times. Our customer has some additional questions.

SerDes supports interfaces and reference clock frequencies listed below (Table 12-195) except Hyperlink.

Can the internal reference clock sources (Table 12-203) be used for all supported interfaces?

Can the external reference clock source (SERDESn_REFCLK_x) be used for all supported interfaces?

Can the reference clock output (PCIE_REFCLKn_x_OUT) be used with all supported interfaces?

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Takuma-san,

Thank you for your support. Sorry for the many times.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Takuma-san,

Thank you for your support. Sorry for the many times.

Our customer wants to first clarify the questions in my previous post. They are concerned that there are differences in how SerDes can be used depending on the interface used.

Daisuke Maeda said:

Can the internal reference clock sources (Table 12-203) be used for all supported interfaces?

Daisuke Maeda said:

Can the external reference clock source (SERDESn_REFCLK_x) be used for all supported interfaces?

Can the reference clock output (PCIE_REFCLKn_x_OUT) be used with all supported interfaces?

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Takuma-san,

Thank you for your reply.

Takuma Fujiwara said:

However, I have not tested other clocks and interfaces, so the best I can do is share above list that I found and ask around internally to see if the other interfaces can be supported from internal refclk.

Could you confirm the combinations of the internal reference clocks and the interfaces that have been tested or can be supported?

Takuma Fujiwara said:

This should work for any interface requiring 100MHz but not for interfaces requiring other clock frequencies. I assume if you get a different oscillator that supports different clock frequency, then the other interfaces can be enabled through external clock.

Could you confirm the combinations of the external reference clock (SERDESn_REFCLK_x) and the interfaces that have been tested or can be supported?

Could you please answer the questions in my post below?

e2e.ti.com/.../4960629

Best regards,

Daisuke

Hi Daisuke-san,

Daisuke Maeda said:

Could you confirm the combinations of the external reference clock (SERDESn_REFCLK_x) and the interfaces that have been tested or can be supported?

The only external reference clock we have is the 100MHz on our EVM. This is a physical part on the EVM, and as such, we can only test the combination of external reference clock with PCIe. I would advise you create a separate E2E thread so that the thread can be reassigned to the hardware team.

Daisuke Maeda said:

Could you confirm the combinations of the internal reference clocks and the interfaces that have been tested or can be supported?

• HFOSC0_CLKOUT - Reserved (not tested) (19.2, 24, 25, 26MHz)
• HFOSC0_CLKOUT - Reserved (not tested) (19.2, 24, 25, 26MHz)
• MAIN_PLL3_HSDIV4_CLKOUT - SGMII/QSGMII/XAUI modes only (125/156.25 MHz)
• MAIN_PLL2_HSDIV4_CLKOUT (100MHz)

These are the combinations tested and not tested. To check with the broader team to see if this has changed, it may take a few weeks.

Daisuke Maeda said:

Could you please answer the questions in my post below?

Please reference our clocking documentation: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html

And also reference our Linux device tree: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi?h=ti-linux-5.10.y#n1121. Specifically, please look at the clocks, clock-names for possible clocks, and assigned-clocks, assigned-clock-parents for the selected clock input.

Regards,

Takuma

Hi Takuma-san,

Thank you for your reply.

I understand that the combinations listed below have been tested.

SERDESn_REFCLK_x - PCIe (100MHz)
MAIN_PLL3_HSDIV4_CLKOUT - SGMII/QSGMII/XAUI modes only (125/156.25 MHz)
MAIN_PLL2_HSDIV4_CLKOUT - PCIe (100MHz)

Is my understanding correct?

Is it correct that 125/156.25 MHz reference clock frequency was used for SGMII and QSGMII?

The reference clock frequency supported for SGMII and QSGMII in Table 12-195 is 100 MHz.

Our customer wants to use PCIe, SGMII, DP and USB3 on their custom boards.

Could you confirm the combinations tested for SGMII, DP and USB3?

Should I create a new thread to inquire about combinations with the external reference clock (SERDESn_REFCLK_x)?

Best regards,

Daisuke

Hi Takuma-san,

Thank you for your reply.

I created new threads for SGMII, DP and USB3 respectively.

AM69: SGMII reference clocks
AM69: DP (Display Port) reference clocks
AM69: USB3 reference clocks

Best regards,

Daisuke

Hi Daisuke-san,

Thank you for creating the new threads. I let the respectively experts know about each thread. As a warning, the USB thread may take a bit longer than the others to be answered, but the other two threads, please expect 1~2 business days.

Regards,

Takuma