Our customer wants to know the tested combinations of interfaces and reference clocks supported by SerDes.
I already got the answer for PCIe.
e2e.ti.com/.../am69-pcie-reference-clocks
SerDes supports interfaces and reference clock frequencies listed below (Table 12-195) except Hyperlink.
The SerDes supports internal reference clock sources listed below (Table 12-203).
J784S4/TDA4AP/TDA4VP/TDA4AH/TDA4VH/AM69A Processors Technical Reference Manual (Rev. C)
Table 12-195. SerDes Supported Standards
Table 12-203. SerDes Internal Reference Clock Selection
Can the MAIN_PLL2_HSDIV4_CLKOUT be used at 100 MHz as an internal reference clock source for USB3?
Can the SERDESn_REFCLK_x be used at 100 MHz as an external reference clock input for USB3?
Best regards,
Daisuke
