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TDA4VH-Q1: Firewall for WKUP_GPIO0

Dengkuan Sun
Prodigy 120 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hi TI Experts

I am trying to use the firewall mechanism to protect the configuration parameters of WKUP_GPIO0 in order that ONLY MCU1_1 can read and write it. I seaching the information for WKUP_GPIO0 in csl_soc_firewalls.h from PDK.

/* Properties of firewall at slave: WKUP_GPIO0_MEM */ 
#define CSL_STD_FW_WKUP_GPIO0_MEM_ID                                                               (132U)                                            (Question: Is this item this firewall ID?)
#define CSL_STD_FW_WKUP_GPIO0_MEM_TYPE                                                             (CSL_FW_SECURITY)              (Question: What is this item?)
#define CSL_STD_FW_WKUP_GPIO0_MEM_MMR_BASE                                                         (0x00000045021000U)        (Question: What is this item? What is the relationship for the start/end address?)
#define CSL_STD_FW_WKUP_GPIO0_MEM_NUM_REGIONS                                                      (1U)                                  (Question: Does this item mean that there is only one region for WKUP_GPIO0?)
#define CSL_STD_FW_WKUP_GPIO0_MEM_NUM_PRIV_IDS_PER_REGION                                          (3U)                     (Question: Does this item mean that there is thress priv slots?)
#define CSL_STD_FW_WKUP_GPIO0_MEM_START                                                            (0x00000042110000U)              (Question: Does this item mean the start address for protecting?)
#define CSL_STD_FW_WKUP_GPIO0_MEM_END                                                              (0x000000421100ffU)                  (Question: Does this item mean the end address for protecting?)
 
Based on the information, I coding the firewall for WKUP_GPIO0 as the following.
int32_t Set_Firewall(void)
{
    int32_t status = CSL_EFAIL;
    uint32_t timeout = 0xFFFFFFFFU;

    struct tisci_msg_fwl_set_firewall_region_resp resp_FW_Wkup_GPIO0 = {0};
    struct tisci_msg_fwl_set_firewall_region_req req_FW_Wkup_GPIO0 = {

        /* Properties of firewall at slave: WKUP_GPIO0 */

        .fwl_id = CSL_STD_FW_WKUP_GPIO0_MEM_ID,
        .region = CSL_STD_FW_WKUP_GPIO0_MEM_NUM_REGIONS,
        .n_permission_regs = 1,
        .control = 0x30A,
        .start_address = CSL_STD_FW_WKUP_GPIO0_MEM_START,
        .end_address = CSL_STD_FW_WKUP_GPIO0_MEM_END,
        .permissions = { 0x61FFFF }  // PrivId 0x61U for MCU1_1

    };

    /* Setting Owner */
    struct tisci_msg_fwl_change_owner_info_req req;
    struct tisci_msg_fwl_change_owner_info_resp resp = {0};


    req.fwl_id = (uint16_t)CSL_STD_FW_WKUP_GPIO0_MEM_ID;
    req.region = CSL_STD_FW_WKUP_GPIO0_MEM_NUM_REGIONS;
    req.owner_index = TISCI_HOST_ID_MCU_0_R5_3; // Cortex R5 context 3 on MCU island(Boot)
   
    status = Sciclient_firewallChangeOwnerInfo(&req, &resp, timeout);
    if (status == CSL_PASS)
    {
        status = Sciclient_firewallSetRegion(&req_FW_Wkup_GPIO0, &resp_FW_Wkup_GPIO0, timeout);
        printf("status2 = %d\n", status);  
    }

    return status;

}
But, when I run this code, the retun status shows the error. Can you help me to find what is wrong.
  • 0
    TI__Guru**** 421845 points

    Hi,

    Can you please tell, which API call is returning error here? Can you also please check TIFS documentation on below link to see if this firewall is not used by TIFS? 

    J784S4 Firewall Descriptions — TISCI User Guide

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 120 points

     Sciclient_firewallChangeOwnerInfo() returns the error. So, the Sciclient_firewallSetRegion is not called.

  • 0 in reply to Dengkuan Sun
    Prodigy 120 points
    In addition, pls reply to these questions. Thanks.
    /* Properties of firewall at slave: WKUP_GPIO0_MEM */ 
    #define CSL_STD_FW_WKUP_GPIO0_MEM_ID                                                               (132U)                                            (Question: Is this item this firewall ID?)
    #define CSL_STD_FW_WKUP_GPIO0_MEM_TYPE                                                             (CSL_FW_SECURITY)              (Question: What is this item?)
    #define CSL_STD_FW_WKUP_GPIO0_MEM_MMR_BASE                                                         (0x00000045021000U)        (Question: What is this item? What is the relationship for the start/end address?)
    #define CSL_STD_FW_WKUP_GPIO0_MEM_NUM_REGIONS                                                      (1U)                                  (Question: Does this item mean that there is only one region for WKUP_GPIO0?)
    #define CSL_STD_FW_WKUP_GPIO0_MEM_NUM_PRIV_IDS_PER_REGION                                          (3U)                     (Question: Does this item mean that there is thress priv slots?)
    #define CSL_STD_FW_WKUP_GPIO0_MEM_START                                                            (0x00000042110000U)              (Question: Does this item mean the start address for protecting?)
    #define CSL_STD_FW_WKUP_GPIO0_MEM_END                                                              (0x000000421100ffU)                  (Question: Does this item mean the end address for protecting?)
  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    Hi,

    The previously provided link has sub links which address many of these questions, including the firewall FAQ.

    Firewall FAQ — TISCI User Guide

    The TDA4VH TRM also contains a firewall chapter in Section 3.2.4 Firewalls(FW).

    A recommended approach to configuring a firewall would be to start with a working example and go from there. 

    Regarding:

    • MEM_ID - Yes this is the Firewall ID
    • MEM_TYPE - TRM defines 3 different types of firewalls (Channel, Master, Peripheral), the CSL_FW_SECURITY is a peripheral firewall.
    • MMR_BASE should align with the Register Description XLS from TDA4VH TRM.  In a quick check this is not the case, however this particular value is not used in the code.
    • NUM_REGIONS - yes 1 region
    • PRIV_ID_PER_REGION - Each region can have up to 3 PrivIds
    • MEM_START - Start of memory range for which firewalls settings should be applied
    • MEM_END - End of memory range for which firewall settings should be applied

    Have you tried above test using TISCI_HOST_ID_MCU_0_R5_1?

    Regards,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Hi KB,

    I have not tried to test using TISCI_HOST_ID_MCU_0_R5_1. However, in my design, this GPIO is used by MCU1_1. So, this is why to use TISCI_HOST_ID_MCU_0_R5_3. 

    Also, for my code, I refer to the example to code it. So, it is strange.

    In addition, does "NUM_REGIONS - yes 1 region" mean that WKUP_GPIO0 works in Region 1?

    Thanks

  • 0 in reply to Dengkuan Sun
    Prodigy 120 points

    Hi,

    Currently, I use the breakpoint to see the return value. You can refer to the following picture. The code is run in mcu1_1

    For running Sciclient_firewallChangeOwnerInfo(&req, &resp, timeout), the resp and req values are shown as following picture. The return is ok.

    For running Sciclient_firewallSetRegion(&req_FW_Wkup_GPIO0, &resp_FW_Wkup_GPIO0, timeout), the return is error.

    Pls check them, give your suggestion.

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    In original post, the Change Owner was failing, what has changed?

    In regards to failing Set call, please try with host Id set to (5) - TISCI_HOST_ID_MCU_0_R5_2, and see if that works.

    Thanks,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Hi KB，

    The following debug information shows the result of TISCI_HOST_ID_MCU_0_R5_2.

    For running Sciclient_firewallChangeOwnerInfo(&req, &resp, timeout), the resp and req values are ok and shown as following picture.

    For running Sciclient_firewallSetRegion(&req_FW_Wkup_GPIO0, &resp_FW_Wkup_GPIO0, timeout), the return is error.

    Pls give your suggestion. Thanks

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    In a previous post it was asked "In addition, does "NUM_REGIONS - yes 1 region" mean that WKUP_GPIO0 works in Region 1?", I had missed this question, and did not note it, until looking at above setting for region.

    The number of regions is 1, however the regions are 0 indexed, please retry test using region 0.

    Thanks,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Thanks KB,

    Another question, how to decide which region is used when a firewall id is set? Where to find a document to describe this? 

    I tested it. Now, both Sciclient_firewallChangeOwnerInfo and Sciclient_firewallSetRegion can work. So, does it mean that WKUP_GPIO0 is set to be configured and read by MCU1_1 ONLY? If no, pls give your addition suggestions.

    In addition, can you suggest how to test the firewall? Should I test it by the method that other cores read, cache and write the registers of WKUP_GPIO0?

    Thanks.

  • 0 in reply to Dengkuan Sun
    Prodigy 120 points

    Addition Question:

    Referring to my code, I use different values to configure the region which is highlighted.

    struct tisci_msg_fwl_set_firewall_region_req req_FW_Wkup_GPIO0 = {

            /* Properties of firewall at slave: WKUP_GPIO0 */

            .fwl_id = CSL_STD_FW_WKUP_GPIO0_MEM_ID,
            .region = 0, //CSL_STD_FW_WKUP_GPIO0_MEM_NUM_REGIONS,
            .n_permission_regs = 1,
            .control = 0x30A,
            .start_address = CSL_STD_FW_WKUP_GPIO0_MEM_START,
            .end_address = CSL_STD_FW_WKUP_GPIO0_MEM_END,
            .permissions = { 0x61FFFF, 0x61FFFF, 0x61FFFF } // PrivId 0x61U

        };
    struct tisci_msg_fwl_change_owner_info_req req;

        req.fwl_id = (uint16_t)CSL_STD_FW_WKUP_GPIO0_MEM_ID;
        req.region = (uint16_t)CSL_STD_FW_WKUP_GPIO0_MEM_NUM_REGIONS;
        req.owner_index = (uint8_t)TISCI_HOST_ID_MCU_0_R5_2; // Cortex R5 context 3 on MCU island(Boot)
    Am I right? If yes, why to have different configuration? If no, should I configure it? For the current test, the return value is pass.
    Thanks
  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    Glad to hear it is working.

    The firewall as shown above will only allow PRIV-ID 0x61, access to memory range CSL_STD_FW_WKUP_GPIO0_MEM_START to CSL_STD_FW_WKUP_GPIO0_MEM_END.

    PrivId 0x61 (97) corresponds to host IDs 5,6

    J784S4 Firewall Descriptions — TISCI User Guide

    J784S4 Host Descriptions — TISCI User Guide

    So yes, only MCU1_1 should have access.   It is always good to test accessing the memory range from other cores, to ensure firewall is working as expected.

    Regarding region number, as that firewall only has 1 region, a value of 0 should be used.

    Regards,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Thanks KB,

    For addition question, how to decide which regions are used when a firewall has more than one region? Do you know where to find the detail description about these information? I have read the TRM and TISCI User Guide, but I found that these document did not enough to direct the user to configure the firewall.

    Thanks

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    You could try looking at the below application note, to see if the example there-in provides some additional information:

    Typical approach is defining background region for full memory, which opens everything up for access, or closes everything down making access restrictive. 

    Overlayed on this background region, fore ground regions are created to open up memory ranges, or close down memory ranges.

    Regards,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Thanks KB,

    I read this document and understood the steps. But I still have some questions about regions. From your answer, full memory can be defined background region which is region 0 defaultly. Then, If I want to limit some memories, I can define foreground region. However, how can I define which foreground region is used? Like the following picture, can you give some detail information about how to define which foreground and background region when a core wants to set a firewall of some memory? Where to find all of necessary configuration information for coding? As the picture shown, which document to show Master 1 can set region 1 as foreground and region 0 as background and Master 2 can set region 2 as background?

    Thanks

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    Hi,

    The setting of firewall values will be different for each solution.   A general approach would be to

    1. identify the regions of memory in the system which are safety critical, security critical, and/or require some level of FFI (Freedom Fom Interference).
    2. Once the regions of memory are known, then, define which initiators/cores should be allowed read/write and/or secure access to this memory range.
    3. With this data defined, then the firewalls can be programmed accordingly.   
    4. Should assistance be required on how to protect a particular memory, then the e2e forums are a good place to ask.

    Regarding above screenshot from TRM, the below text is present:

    In the above case, Region 0 and Region 2 are background regions (background bit set in control register).
    Region 1, Region 3 and Region 4 are not background (foreground) regions. In case the incoming transaction
    hits in address in Region 1, the permissions of Region 1 are applied to filter incoming transaction, thereby
    completely ignoring the permission of the background Region 0.

    In this example the memory has been split into 2 background regions Region 0 / Region 2, and is defining how 3 different initiators are allowed to access this memory.

    Region 0:

    • Region 0, Non secure R/W, for Initiator1 
    • Region 1, Overlays Region 0, to make this lower memory range Secure R/W for Initiator 1 only
    • Region 3, Overlays Region 0, to make this lower memory range
      • Non Secure R/W for Initiator 3,
      • Non Secure R only for Initiator 2.

    Region 2:

    • Region 2, Non Secure R/W for Initiator 2
    • Region 4, Overlays Region 2, to allow
      • Secure R/W for Initiator 1,
      • Non-Secure R only for Initiator 1

    Regards,

    kb

    Regards,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Thanks KB

    I would like to know what the return value is when I try to read the registers of WKUP_GPIO0 after I configure the firewall of WKUP_GPIO0 which is only read/written/cachable by MCU1_1.

    Currently, I tested this by that the funcitoin GPIOPinRead_v0 read the register 0x4211000F in MCU2_0. And the fuction is blocked. But, the function can run when I do not set the firewall. Therefore, I think that the firewall is set correctly. But, I did not make sure this. Can you help to confirm this?

    Thanks

    Dengkuan

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    Hi Dengkuan,

    Another way to verify, is to check if a firewall log has been generated, this can be done by following below FAQ to enable additional logging:

    Should a firewall log occur, it can be decoded as per below link.

    In regards to behavior on MCU2_0 the R5 core would likely take an exception, similar to accessing an address that does not exist.

    Regards,

    kb

  • 0 in reply to KB
    Prodigy 120 points

    Thanks KB,

    Except the method, whether to have other ways to test, such writing some test codes?

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    Hi,

    The method you had described above is the method for testing:

    • Enable firewall
      • Try accessing (R/W etc) the memory ranges defined by the regions from different initiators, to test that firewall is behaving as expected.
    • Disable firewall
      • Try accessing (R/W etc) the memory ranges defined by the regions from different initiators, to test that firewall is behaving as expected.

    For design/debug testing, if using a H/W debugger, it is possible to connect to a particular core, then access memory from that core.  In this case the core would be the initiator.

    Regards,

    kb

  • +1 in reply to KB
    Prodigy 120 points

    Hi Kb，

    Have another question: What does "Privileged/User mode" mean? What is the difference for two options? I did not find the document for describing this configuration.

    Thanks

  • 0 in reply to Dengkuan Sun
    TI__Guru** 101381 points

    Hi,

    The use of user vs privelege is a form of access control, and possibly would tie into the security solution.

    Each transaction from an initiator can be identified as having user or privileged mode attributes.  Hardware deemed critical, such as system configuration registers, could include restrictions that register contents may only be modified when in privileged modes of operation. User mode would be intended for individual tasks and does not give as much access.

    ARM documentation offers many articles / discussions on this.

    For any further details which are required, please open a separate e2e.

    Regards,

    kb