AM6422: Enable the MCU RTI_WDT in R5 SPL

xixiguohx

Part Number: AM6422

We used AM6422 customized board, and we want to enable the MCU RTI_WDT in R5 SPL. When it block in R5 SPL, the MCU RTI_WDT can reset the system.

What I did now is as below,

Dts,

In k3-am64-mcu.dtsi
mcu_rti1: rti@40610000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x40610000 0x0 0x100>;
		clocks = <&k3_clks 135 0>;
		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
		assigned-clocks = <&k3_clks 135 0>;
		assigned-clock-parents = <&k3_clks 135 4>;
	};

R5 config,

CONFIG_SPL_WATCHDOG_SUPPORT=y

CONFIG_SYSRESET=y

CONFIG_SPL_SYSRESET=y

CONFIG_SYSRESET_TI_SCI=y

CONFIG_SYSRESET_WATCHDOG=y

CONFIG_WATCHDOG=y

CONFIG_WATCHDOG_TIMEOUT_MSECS=60000

CONFIG_WDT=y

CONFIG_WDT_K3_RTI=y

CONFIG_SPL_WDT=y

But got:

U-Boot SPL 2021.01-g7653b040e1 (Jan 18 2024 - 10:31:13 +0000)
Resetting on cold boot to workaround ErrataID:i2331
resetting ...

U-Boot SPL 2021.01-g7653b040e1 (Jan 18 2024 - 10:31:13 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
SPL initial stack usage: 13376 bytes
WDT: Not found!
Trying to boot from SPI
Starting ATF on ARM64 core...

It seems can not find device RTI_WDT.

over 1 year ago

0 Nick Saulnier over 1 year ago

TI__Guru** 100750 points

Hello xixiguohx,

It looks like this is a followup on your thread https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1292546/am6422-how-to-configure-rti-watchdog-expire-to-reset-system/4910002#4910002.

Can you comment a bit on your design process here? Is there a specific reason you are looking at the MCU RTI?

Regards,

Nick

0 xixiguohx over 1 year ago in reply to Nick Saulnier

Intellectual 720 points

Hi Nick,

The previous thread is to enable the RTI_WDT in kernel and to monitor the process after kernel RTI_WDT was initialized. And we also want to monitor the startup process in R5 SPL. This is because that we found in one of our customized board, it will block in R5 SPL sometimes like below,

[22_14:25:57]U-Boot SPL 2021.01-g3848e80346 (Jan 19 2024 - 04:26:19 +0000)
[22_14:25:57]Resetting on cold boot to workaround ErrataID:i2331
[22_14:25:57]resetting ...
[22_14:25:57]
[22_14:25:57]U-Boot SPL 2021.01-g3848e80346 (Jan 19 2024 - 04:26:19 +0000)
[22_14:25:57]SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
[22_14:25:58]SPL initial stack usage: 13384 bytes

We want to add MCU RTI_WDT before the block, so when block will trigger MCU RTI_WDT to do reset.

Best Regards
xixiguohx

0 Hong Guan64 over 1 year ago in reply to xixiguohx

TI__Guru 68290 points

Hello Xiao,
Here are some caveats on RTI_WDT:
- RTI_WDT timeout value can be configured once per SoC RESET
- I'm not aware of support on patting RTI_WDT @SPL/u-boot level.
I think a bit challenging to enable your user case.

Best,
-Hong

0 xixiguohx over 1 year ago in reply to Hong Guan64

Intellectual 720 points

Hi Hong，

Thank you. Yes, I understand that the RTI_WDT timeout value can be configured once per SoC RESET. That is the reason I want to enable MCU RTI_WDT in R5 SPL, because of we have already used the main RTI_WDT in kernel.

Is there any plan to enable the RTI_WDT @SPL level in your side?

Best Regards

xixiguohx

0 Hong Guan64 over 1 year ago in reply to xixiguohx

TI__Guru 68290 points

Hello Xiao,
In the referenced e2e.
e2e.ti.com/.../4822059
I'm able to fire off main domain RTI_WDT RTI0 @u-boot to starts to count-down.
- For the user case of SPL/u-boot lockup, "RTI_WDT timeout => MCU ESM => WarmReset" would be helpful...
- But for the normal boot senario, I'm not aware of support on patting RTI_WDT @SPL/u-boot level.
Best,
-Hong

0 xixiguohx over 1 year ago in reply to Hong Guan64

Intellectual 720 points

Hi Hong,

Ok, thanks!

Best Regards

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AM6422: Enable the MCU RTI_WDT in R5 SPL