AM625: AM6254 LPDDR4 Interfacing

Paul Nwoko

Part Number: AM625

Hello all,

I am working on a custom board with the AM6254ATCGGAALW SoC and interfacing it with an LPDDR4 RAM chip. The LPDDR4 address bus is only 6bit wide, and it is connected to the first 6 bits in the soc DDR_A port and the rest are left unconnected. Is this connection correct? The LPDDR4 RAM part number is MT53E1G16D1FW046AITA.

How do I handle the unused address lines on the SoC?

Any performance implication for this configuration?

Regards,

Paul Nwoko.

over 1 year ago

+1 JJD over 1 year ago

TI__Guru* 80390 points

yes, please refer to the DDR layout guidelines app note: https://www.ti.com/lit/pdf/sprad06 when designing the DDR portion of your board. The controller supports both DDR4 and LPDDR4, which is the reason for the extra address signals. When using LPDDR4, these extra address signals are unused and can be left as no connects.

Regards,

James

0 Paul Nwoko over 1 year ago in reply to JJD

Prodigy 105 points

Alight,

Thank you.

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AM625: AM6254 LPDDR4 Interfacing