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AM6442: 25MHz Crystal logic level for HFOSC

Part Number: AM6442


Hello,
I'm trying to double check the margin leve I've got on MCU_OSC0_XI level. I've followed all recommendations and computations on CL1 & CL2.

So according to table 7.7.3 of sprsp56f_Datasheet am6442 Sept 2022 revF.pdf , it seems that Vihmin is about 0.65 x 1.8 = 1.17V

I've put passive probe (Cl=3.9pF), which I know may degrade a little bit the signal, to check signal level, and maximum level is about 1V => Vihmin is never reached.... but it works fine.

I don't understand how it could work.

I wonder if there is not something related to this sentence : 

My assumption : in fact, due to MCU_OSC0_XI AC coupling, we just have to respect VHYS (=typ 49mV), and MCU_OSC0_XI should have a min swing of VHSYS .


What are input level threshold on HFOSC?

Thanks for your help.

  • It sounds like you are trying to apply digital logic level thresholds to the HFOSC input when using a crystal circuit. The oscillator is an analog circuit. When operating with a crystal circuit the voltage across the crystal circuit is being monitored by an internal automatic gain control circuit and the amplifier gain is adjusted to maintain an oscillation amplitude that is large enough to provide a valid reference clock without over-driving the crystal. You do not need to worry with checking the amplitude as long as you selected the crystal components as described in the datasheet.

    We do not expect customers to validate margin when operating with a crystal circuit because we have already built-in enough margin as long as you follow the crystal circuit recommendations. However, it sounds like you have margin If the oscillator was able to start oscillation with the additional loading of the scope probe.

    The digital levels provided in the datasheet only apply when sourcing a reference clock from an LVCMOS clock source.

    Regards,
    Paul