Hi TI,
I am using vanilla PSDK Linux v09.01 on TI EVM. I want to change U-Boot console output from MAIN_UART0 to MAIN_UART4. I did the following changes in U-Boot Repo:
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index fffe33bc72..10e0114d07 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -8,7 +8,7 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = "serial6:115200n8";
tick-timer = &timer1;
};
@@ -114,7 +114,7 @@
bootph-pre-ram;
};
-&main_uart0 {
+&main_uart4 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index b9bc6dccb8..8e29562bc8 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -13,27 +13,8 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
- };
-
- gpio_keys: gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
-
- sw10: sw10 {
- label = "GPIO Key USER1";
- linux,code = <BTN_0>;
- gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
- };
-
- sw11: sw11 {
- label = "GPIO Key USER2";
- linux,code = <BTN_1>;
- gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
- };
+ stdout-path = "serial6:115200n8";
+ bootargs = "console=ttyS6,115200n8 earlycon=ns16550a,mmio32,0x02840000";
};
evm_12v0: fixedregulator-evm12v0 {
@@ -117,6 +98,13 @@
J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
>;
};
+
+ myuart4_pins_default: myuart4_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
+ J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
+ >;
+ };
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
@@ -263,7 +251,8 @@
};
&main_uart0 {
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ /* UART not brought out */
+ status = "disabled";
};
&main_uart3 {
@@ -271,6 +260,13 @@
status = "disabled";
};
+&main_uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&myuart4_pins_default>;
+ status = "okay";
+ power-domains = <&k3_pds 281 TI_SCI_PD_SHARED>;
+};
+
&main_uart5 {
/* UART not brought out */
status = "disabled";
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 45c3f3821e..3cf67b3627 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -15,10 +15,11 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
+ serial6 = &main_uart4;
};
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = "serial6:115200n8";
tick-timer = &timer1;
};
@@ -191,6 +192,22 @@
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
+
+ myuart2_pins_default: myuart2_pins_default {
+ bootph-pre-ram;
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
+ J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
+ >;
+ };
+
+ myuart4_pins_default: myuart4_pins_default {
+ bootph-pre-ram;
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
+ J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
+ >;
+ };
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
@@ -244,10 +261,18 @@
};
&main_uart0 {
+ status = "disabled";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
+ pinctrl-0 = <&myuart4_pins_default>;
status = "okay";
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ power-domains = <&k3_pds 281 TI_SCI_PD_SHARED>;
};
&main_sdhci0 {
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 89344a4b24..a6ec56873e 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -18,7 +18,7 @@
};
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = "serial6:115200n8";
tick-timer = &timer1;
};
diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts
index 847ff73431..8a056081cb 100644
--- a/arch/arm/dts/k3-j721e-sk.dts
+++ b/arch/arm/dts/k3-j721e-sk.dts
@@ -15,8 +15,8 @@
model = "Texas Instruments J721E SK A72";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = "serial6:115200n8";
+ bootargs = "console=ttyS6,115200n8 earlycon=ns16550a,mmio32,0x02840000";
};
memory@80000000 {
@@ -833,3 +833,138 @@
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
+
+&main_gpio0 {
+ gpio0-7-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_7";
+ };
+
+ gpio0-71-hog {
+ gpio-hog;
+ gpios = <71 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_71";
+ };
+
+ gpio0-82-hog {
+ gpio-hog;
+ gpios = <82 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_82";
+ };
+
+ gpio0-11-hog {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_11";
+ };
+
+ gpio0-101-hog {
+ gpio-hog;
+ gpios = <101 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_101";
+ };
+
+ gpio0-107-hog {
+ gpio-hog;
+ gpios = <107 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_107";
+ };
+
+ gpio0-103-hog {
+ gpio-hog;
+ gpios = <103 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_103";
+ };
+
+ gpio0-2-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_2";
+ };
+
+ gpio0-115-hog {
+ gpio-hog;
+ gpios = <115 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_115";
+ };
+
+ gpio0-70-hog {
+ gpio-hog;
+ gpios = <70 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_70";
+ };
+
+ gpio0-81-hog {
+ gpio-hog;
+ gpios = <81 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_81";
+ };
+
+ gpio0-1-hog {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_1";
+ };
+
+ gpio0-5-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_5";
+ };
+
+ gpio0-8-hog {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_8";
+ };
+
+ gpio0-102-hog {
+ gpio-hog;
+ gpios = <102 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_102";
+ };
+
+ gpio0-108-hog {
+ gpio-hog;
+ gpios = <108 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_108";
+ };
+
+ gpio0-97-hog {
+ gpio-hog;
+ gpios = <97 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_97";
+ };
+
+ gpio0-3-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_3";
+ };
+
+ gpio0-4-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "GPIO0_4";
+ };
+};
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index ca53b43962..72c8f27f3e 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -14,6 +14,7 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_hardware.h"
+#include "j721e_qos_params.h"
#endif
#ifdef CONFIG_SOC_K3_J721S2
diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c
index e887889e2f..1f78547608 100644
--- a/arch/arm/mach-k3/j721e/clk-data.c
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -595,6 +595,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
CLK_DIV("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0),
+ CLK_DIV("usart_programmable_clock_divider_out4", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d0, 0, 2, 0, 0),
CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0, 0),
CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
@@ -769,6 +770,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"),
DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(281, 0, "usart_programmable_clock_divider_out4"),
+ DEV_CLK(281, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -792,7 +795,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j721e_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 158,
+ .clk_list_cnt = 159,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 176,
+ .soc_dev_clk_data_cnt = 178,
};
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
index e5e2a2a5df..28665a746b 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -47,6 +47,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(146, &soc_lpsc_list[1]),
PSC_DEV(279, &soc_lpsc_list[1]),
+ PSC_DEV(281, &soc_lpsc_list[1]),
PSC_DEV(90, &soc_lpsc_list[2]),
PSC_DEV(47, &soc_lpsc_list[3]),
PSC_DEV(288, &soc_lpsc_list[4]),
@@ -76,5 +77,5 @@ const struct ti_k3_pd_platdata j721e_pd_platdata = {
.num_psc = 2,
.num_pd = 5,
.num_lpsc = 16,
- .num_devs = 23,
+ .num_devs = 24,
};
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index fb36574a9a..ec0d976691 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -193,6 +193,277 @@ void do_dt_magic(void)
}
#endif
+void setup_navss_nb(void)
+{
+ /* Map orderid 8-15 to VBUSM.C thread 2 (real-time traffic) */
+ writel(2, NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
+void setup_vpac_qos(void)
+{
+ unsigned int channel, group;
+
+ /* vpac data master 0 */
+ for (channel = 0; channel < QOS_VPAC0_DATA0_NUM_I_CH; ++channel) {
+
+ writel((QOS_VPAC0_DATA0_ATYPE << 28), (uintptr_t)QOS_VPAC0_DATA0_CBASS_MAP(channel));
+ }
+
+ /* vpac data master 1 */
+ for (channel = 0; channel < QOS_VPAC0_DATA1_NUM_I_CH; ++channel) {
+
+ writel((QOS_VPAC0_DATA1_ATYPE << 28), (uintptr_t)QOS_VPAC0_DATA1_CBASS_MAP(channel));
+ }
+
+ /* vpac ldc0 */
+ for (group = 0; group < QOS_VPAC0_LDC0_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_VPAC0_LDC0_NUM_I_CH; ++channel) {
+
+ writel((QOS_VPAC0_LDC0_ATYPE << 28) | (QOS_VPAC0_LDC0_PRIORITY << 12) | (QOS_VPAC0_LDC0_ORDER_ID << 4), (uintptr_t)QOS_VPAC0_LDC0_CBASS_MAP(channel));
+ }
+
+}
+
+void setup_dmpac_qos(void)
+{
+ unsigned int channel;
+
+ /* dmpac data */
+ for (channel = 0; channel < QOS_DMPAC0_DATA_NUM_I_CH; ++channel) {
+
+ writel((QOS_DMPAC0_DATA_ATYPE << 28), (uintptr_t)QOS_DMPAC0_DATA_CBASS_MAP(channel));
+ }
+}
+
+void setup_dss_qos(void)
+{
+ unsigned int channel, group;
+
+ /* two master ports: dma and fbdc */
+ /* two groups: SRAM and DDR */
+ /* 10 channels: (pipe << 1) | is_second_buffer */
+
+ /* master port 1 (dma) */
+ for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel) {
+
+ writel((QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4), (uintptr_t)QOS_DSS0_DMA_CBASS_MAP(channel));
+ }
+
+ /* master port 2 (fbdc) */
+ for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel) {
+
+ writel((QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4), (uintptr_t)QOS_DSS0_FBDC_CBASS_MAP(channel));
+ }
+}
+
+void setup_gpu_qos(void)
+{
+ unsigned int channel, group;
+
+ /* gpu m0 rd */
+ for (group = 0; group < QOS_GPU0_M0_RD_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M0_RD_NUM_I_CH; ++channel) {
+
+ if(channel == 0)
+ {
+ writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel));
+ }
+ else
+ {
+ writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel));
+ }
+ }
+
+ /* gpu m0 wr */
+ for (group = 0; group < QOS_GPU0_M0_WR_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M0_WR_NUM_I_CH; ++channel) {
+
+ writel((QOS_GPU0_M0_WR_ATYPE << 28) | (QOS_GPU0_M0_WR_PRIORITY << 12) | (QOS_GPU0_M0_WR_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_WR_CBASS_MAP(channel));
+ }
+
+ /* gpu m1 rd */
+ for (group = 0; group < QOS_GPU0_M1_RD_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M1_RD_NUM_I_CH; ++channel) {
+
+ if(channel == 0)
+ {
+ writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel));
+ }
+ else
+ {
+ writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel));
+ }
+ }
+
+ /* gpu m1 wr */
+ for (group = 0; group < QOS_GPU0_M1_WR_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M1_WR_NUM_I_CH; ++channel) {
+
+ writel((QOS_GPU0_M1_WR_ATYPE << 28) | (QOS_GPU0_M1_WR_PRIORITY << 12) | (QOS_GPU0_M1_WR_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_WR_CBASS_MAP(channel));
+ }
+}
+
+void setup_encoder_qos(void)
+{
+ unsigned int channel, group;
+
+ /* encoder rd */
+ for (group = 0; group < QOS_ENCODER0_RD_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_ENCODER0_RD_NUM_I_CH; ++channel) {
+
+ writel((QOS_ENCODER0_RD_ATYPE << 28) | (QOS_ENCODER0_RD_PRIORITY << 12) | (QOS_ENCODER0_RD_ORDER_ID << 4), (uintptr_t)QOS_ENCODER0_RD_CBASS_MAP(channel));
+ }
+
+ /* encoder wr */
+ for (group = 0; group < QOS_ENCODER0_WR_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_ENCODER0_WR_NUM_I_CH; ++channel) {
+
+ writel((QOS_ENCODER0_WR_ATYPE << 28) | (QOS_ENCODER0_WR_PRIORITY << 12) | (QOS_ENCODER0_WR_ORDER_ID << 4), (uintptr_t)QOS_ENCODER0_WR_CBASS_MAP(channel));
+ }
+}
+
+void setup_decoder_qos(void)
+{
+ unsigned int channel, group;
+
+ /* decoder rd */
+ for (group = 0; group < QOS_DECODER0_RD_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_DECODER0_RD_NUM_I_CH; ++channel) {
+
+ writel((QOS_DECODER0_RD_ATYPE << 28) | (QOS_DECODER0_RD_PRIORITY << 12) | (QOS_DECODER0_RD_ORDER_ID << 4), (uintptr_t)QOS_DECODER0_RD_CBASS_MAP(channel));
+ }
+
+ /* decoder wr */
+ for (group = 0; group < QOS_DECODER0_WR_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_DECODER0_WR_NUM_I_CH; ++channel) {
+
+ writel((QOS_DECODER0_WR_ATYPE << 28) | (QOS_DECODER0_WR_PRIORITY << 12) | (QOS_DECODER0_WR_ORDER_ID << 4), (uintptr_t)QOS_DECODER0_WR_CBASS_MAP(channel));
+ }
+}
+
+void setup_c66_qos(void)
+{
+ unsigned int channel, group;
+
+ /* c66_0 mdma */
+ for (group = 0; group < QOS_C66SS0_MDMA_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_C66SS0_MDMA_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_C66SS0_MDMA_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_C66SS0_MDMA_NUM_I_CH; ++channel) {
+
+ writel((QOS_C66SS0_MDMA_ATYPE << 28) | (QOS_C66SS0_MDMA_PRIORITY << 12) | (QOS_C66SS0_MDMA_ORDER_ID << 4), (uintptr_t)QOS_C66SS0_MDMA_CBASS_MAP(channel));
+ }
+
+ /* c66_1 mdma */
+ for (group = 0; group < QOS_C66SS1_MDMA_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_C66SS1_MDMA_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_C66SS1_MDMA_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_C66SS1_MDMA_NUM_I_CH; ++channel) {
+
+ writel((QOS_C66SS1_MDMA_ATYPE << 28) | (QOS_C66SS1_MDMA_PRIORITY << 12) | (QOS_C66SS1_MDMA_ORDER_ID << 4), (uintptr_t)QOS_C66SS1_MDMA_CBASS_MAP(channel));
+ }
+}
+
+void setup_main_r5f_qos(void)
+{
+ unsigned int channel, group;
+
+ /* R5FSS0 core0 - read */
+ for (group = 0; group < QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel) {
+
+ writel((QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel));
+ }
+
+ /* R5FSS0 core0 - write */
+ for (group = 0; group < QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel) {
+
+ writel((QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel));
+ }
+
+ /* R5FSS0 core1 - read */
+ for (group = 0; group < QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel) {
+
+ writel((QOS_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel));
+ }
+
+ /* R5FSS0 core1 - write */
+ for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group) {
+ writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group));
+ writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group));
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel) {
+
+ writel((QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel));
+ }
+
+}
+
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
@@ -289,6 +560,18 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
+
+ if (soc_is_j721e()) {
+ setup_navss_nb();
+ setup_c66_qos();
+ setup_main_r5f_qos();
+ setup_vpac_qos();
+ setup_dmpac_qos();
+ setup_dss_qos();
+ setup_gpu_qos();
+ setup_encoder_qos();
+ }
+
spl_enable_dcache();
}
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 4f91859c2e..d54f9a9e63 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -25,8 +25,8 @@ findfdt=
setenv name_fdt ti/k3-j721e-sk.dtb; fi;
setenv fdtfile ${name_fdt}
name_kern=Image
-console=ttyS2,115200n8
-args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000
+console=ttyS6,115200n8
+args_all=setenv optargs earlycon=ns16550a,mmio32,0x02840000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index cd2475f43f..6ce639fd89 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -24,6 +24,7 @@ CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_GPIO_HOG=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 75d13df8ad..548579262c 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -608,6 +608,23 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
writel(val, base + DDRSS_ECC_CTRL_REG);
}
+#ifdef CONFIG_K3_J721E_DDRSS
+#define DDRSS_V2A_LPT_DEF_PRI_MAP_REG (0x02980030u)
+#define DDRSS_V2A_HPT_DEF_PRI_MAP_REG (0x0298004Cu)
+#define DDRSS_V2A_LPT_HPT_PRI_MAP_VAL (0x77777777u)
+
+void j721e_lpddr4_priority_map(void)
+{
+ /* Override defaults with a flattened priority */
+ /* This makes VBUSM.C priority take effect */
+ /* LPT */
+ writel(DDRSS_V2A_LPT_HPT_PRI_MAP_VAL, (uintptr_t)DDRSS_V2A_LPT_DEF_PRI_MAP_REG);
+
+ /* HPT */
+ writel(DDRSS_V2A_LPT_HPT_PRI_MAP_VAL, (uintptr_t)DDRSS_V2A_HPT_DEF_PRI_MAP_REG);
+}
+#endif
+
static int k3_ddrss_probe(struct udevice *dev)
{
int ret;
@@ -640,6 +657,10 @@ static int k3_ddrss_probe(struct udevice *dev)
if (ret)
return ret;
+#ifdef CONFIG_K3_J721E_DDRSS
+ j721e_lpddr4_priority_map();
+#endif
+
k3_lpddr4_start(ddrss);
if (ddrss->ti_ecc_enabled) {
Unfortunately, there were some uncommited changes, which make the diff a little confusing. The most relevant changes concern the following files:
- /arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
- /arch/arm/dts/k3-j721e-common-proc-board.dts
- /arch/arm/dts/k3-j721e-r5-common-proc-board.dts
- /arch/arm/mach-k3/include/mach/hardware.h
- /arch/arm/mach-k3/j721e/clk-data.c
- /arch/arm/mach-k3/j721e/dev-data.c
I did not modify ATF, so the logs from there will still go to MAIN_UART0. The log output on MAIN_UART4 with the previous mentioned changes is the following:
Welcome to minicom 2.8 OPTIONS: I18n Port /dev/ttyUSB3, 09:39:39 Press CTRL-A Z for help on special keys Core: 126 devices, 35 uclasses, devicetree: separate Flash: 0 Bytes MMC: mmc@4f80000: 0, mmc@4fb0000: 1 Loading Environment from nowhere... OK In: serial@2840000 Out: serial@2840000 Err: serial@2840000 am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000 Detected: J7X-BASE-CPB rev E3 Detected: J7X-VSC8514-ETH rev E2 cdns,sierra serdes@5000000: sierra probed Net: eth0: ethernet@46000000port@1 Hit any key to stop autoboot: 0 =>
So I do not get any logs from R5 SPL.
I think the root cause is the missing/wrong clk/dev information in clk-data.c and dev-data.c. The changes I made were based on the information on existing UART clks, so there could be easily someting wrong.
Could you please verify on your end that you are getting the same output? And could you please provide a correct clk-data.c/dev-data.c? Even better would be a safe way to generate this file on my end, since on our custom hardware, we only have MAIN_UART6 available for U-Boot and Linux, which would need similar changes like the ones for MAIN_UART4.
Thanks for your help and best regards,
Felix
