Greetings!
In Section 7.4.7 of the TRM for this family of processors (Literature #SPRUIV7B), it names two UART peripherals as part of the PRUSS subsystem (PRUSS0_UART0 and PRUSS1_UART0).
In page 2 of the datasheet (Literature #SPRSP58B), it likewise says "UARTs" under the PRU Subsystem heading, implying that there is more than one.
My confusion comes from locating the signals/pin to access both of the UARTs in the PRUSS subsystem. In Section 6.3.21 of the datasheet, Table 6-50, I can see the signal descriptions of UART for PRUSS0. In Table 6-51, however, I cannot see descriptions of UART for PRUSS1.
Does this family of processors support two UARTs in the PRUSS subsystem? Where may I find the needed information to interface with it?
Thanks for your time.