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SPI port on Omap-L138

Other Parts Discussed in Thread: OMAP-L138

Dear E2E:

I have the question about Omap-L138 SPI port.

Reading User's Guide (SPRUFM41 of 3/2011) I found on page14:  in "Chip Select Hold Option":

"If the chip select hold option is enabled, the chip select will not toggle between two consecutive accesses".

And also on page44 - SPIDAT1 register: CSHOD ='1' and WDEL = '0' - means no delays will be inserted in the consecutive transfers and CS will hold active.

Is this correct?

1.  I need to transfer 144 bits from A/D converter to DSP Omap-L138 using SPI port.

2.  It looks like the above settings CSHOD ='1' and WDEL = '0' should work.

3.  But how can I specify the length of the transfer? If format is set to 16 bits - I need to transfer 9 words.

4.  On page44, SPIDAT1 register, in the table: "The chip select signal is held active at the end of a transfer until a control field with new data and control information is loaded into SPIDAT1. If the new chip select hold information equals the previous one, the active chip select signal is extended until the end of transfer with CSHOLD cleared"

5.  That means - the SW must write the new information into SPIDAT1 register during the last 16-bit transfer to terminate the transfer. Is this correct?

6.  If this is correct - the SW must be very involved counting the number of the transfers. Using the DMA became a little difficult.

7.  Will it be OK to set DMA for the 8 16-bit transfers and then when DMA is completed - write into SPIDAT1 register for the last 9-th transfer? Will this work?

8.  Is there the better way to transfer 144 bits (9 16-bit words) using SPI port on Omap-L138?

Thank you for your help,

Boris Ruvinsky

 

  • Boris,

    This question is more suited for the OMAP forum as you're asking about the L138's peripherals. I'll move the post to the appropriate forum shortly...

  • Hi Kevin.

    Thank you for moving my request to Omap-L138 forum.

    But I still have no respond on my questions.

    Is my request in the right place?

    I am adding my questions again here:

    Dear E2E:

    I have the question about Omap-L138 SPI port.

    Reading User's Guide (SPRUFM41 of 3/2011) I found on page14:  in "Chip Select Hold Option":

    "If the chip select hold option is enabled, the chip select will not toggle between two consecutive accesses".

    And also on page44 - SPIDAT1 register: CSHOD ='1' and WDEL = '0' - means no delays will be inserted in the consecutive transfers and CS will hold active.

    Is this correct?

    1.  I need to transfer 144 bits from A/D converter to DSP Omap-L138 using SPI port.

    2.  It looks like the above settings CSHOD ='1' and WDEL = '0' should work.

    3.  But how can I specify the length of the transfer? If format is set to 16 bits - I need to transfer 9 words.

    4.  On page44, SPIDAT1 register, in the table: "The chip select signal is held active at the end of a transfer until a control field with new data and control information is loaded into SPIDAT1. If the new chip select hold information equals the previous one, the active chip select signal is extended until the end of transfer with CSHOLD cleared"

    5.  That means - the SW must write the new information into SPIDAT1 register during the last 16-bit transfer to terminate the transfer. Is this correct?

    6.  If this is correct - the SW must be very involved counting the number of the transfers. Using the DMA became a little difficult.

    7.  Will it be OK to set DMA for the 8 16-bit transfers and then when DMA is completed - write into SPIDAT1 register for the last 9-th transfer? Will this work?

    8.  Is there the better way to transfer 144 bits (9 16-bit words) using SPI port on Omap-L138?

    Thank you for your help,

    Boris Ruvinsky

    Thank you,

    Boris Ruvinsky

  • Boris,

    here are some answers to your questions.

    3.  If you are going to use the CPU to perform the writes you can simply write first word w/CSHOLD on + write 7 16b words to the SPIDAT1 register (without changing the control bits in the upper 16b of the register) and on the last write to SPIDAT1 you turn off the CSHOLD.  You can use a temporary variable to preload the first 32b value of SPIDAT1 with the CSHOLD on outside of your loop and the last write w/the CSHOLD off.

    5. correct

    6. correct.

    7.  yes that should be ok and it should work, however #3 above should be easier to implement

    8.  you have the right idea.

    regards,

    miguel

     

  • Hi Miguel.

    Thank you very much for your respond and help.

    I have one more question aboutSPI interface on OMAP-L138.

    1.  SPI_CLK is determing by Prescaler value:  SPI_CLK_freq = "SPI module clock"/(PRESCALE+1).

     When (PRESCALE+1) is not "even" value - SPI_CLK is not 50% duty cycle. Is it correct?

    I use CLK POLARITY = 0 and I have (PRESCALE+1) = 5. I expect the SPI_CLK duty cycle to be 60% for "CLK high" and 40% for "CLK low".

    Is this correct? I could not find it in the data sheet and User Guide.

    Thank you,

    Boris Ruvinsky

  •   Hi Miguel,

    Thank you very much for your respond and help.

    I post this question as a new post also and replaying to you to make sure you can get this request.

    I have two more question about SPI interface on OMAP-L138.

    1.  SPI_CLK is determine by Prescaler value:  SPI_CLK_freq = "SPI module clock"/(PRESCALE+1).

     When (PRESCALE+1) is not "even" value - SPI_CLK is not 50% duty cycle. Is it correct?

    I use CLK POLARITY = 0 and I have (PRESCALE+1) = 5. I expect the SPI_CLK duty cycle to be 60% for "CLK high" and 40% for "CLK low".

    Is this correct? I could not find it in the data sheet and User Guide.

    2.  I use 4-wire interface with Enable. I need to tramsfer 4x16-bit words without any delays between transfers. Is CSHOLD bit  in reg SPIDAT1 applicable in 4-wire mode with ENABLE? ENABLE will stay active (low) for the sufficient time and I will set CSHOLD=1 and WDEL=0 in SPIDAT1 register.

    Thank you,

    Boris Ruvinsky

  • Boris,

    i'm looking at this for you as i don't have the answer at the top of my head.

    regards,

    miguel

  • Boris,

    on #1.  I am fairly confident that the SPI Duty cycle is 50% for even/odd Prescale values.  I'm triple checking with module owner to re-confirm :).  I've checked it on the bench and it is 50% in both cases. 

    on #2.  I think what you are describing is the 5-pin mode rather than 4pin mode as explained in the Technical Ref manual http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf (section 30.2.10 SPI Operation: 5-Pin Mode, and inside the CSHOLD bit description in Table 30-21), in which case the CSHOLD Bit is applicable as well only when the SPI is in master mode. 

    regards,

    miguel

  • Dear Boris

    I am also working on similar lines...I need to connect ADC to SPI of OMAP-L138..I am new to DSPs..can you help by providing some kind of design flow/document...

    I need to connect 4 channel analog audio to my DSP....

    Regards

    Hemant