TDA4VM-Q1: DDR init fail in SBL

xie jc

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Hello TI engineers,

We have produced approximately 2000 boards of TDA4 and identified two machines with abnormal startup, while the others are functioning normally. Analysis indicates that the exception occurs during SBL initialization of DDR.

First faulty machine:

The handshake time with the DDR controller is unusually long, taking about 10 seconds. Although the handshake eventually succeeds, the board exhibits abnormal startup.

Fullscreen 03_sbl_ddr_int_toolong.log Download

SBL Revision: 01.00.10.01 (Jan 22 2024 - 15:05:30)
TIFS  ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...Board_DDRProbe: PASS
Board_DDRInitDrv: PASS
--->>> LPDDR4 Initialization is in progress ... <<<---
Reg Value: 128
Frequency Change type 1 request from Controller
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Reg Value: 128
Frequency Change type 2 request from Controller
--->>> Frequency Change request handshake is completed... <<<---
LPDDR4_Start: PASS
done.
Initializing SERDES ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Searching for X509 certificate ...not found
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x41010000
Copying 0x490 bytes to 0x41010040
Copying 0x448 bytes to 0x410104d0
Copying 0x318 bytes to 0x41010918
Copying 0x118 bytes to 0x41010c30
Copying 0x8c bytes to 0xa0100000
Copying 0x1684 bytes to 0xa058d400
Copying 0x538 bytes to 0xa058ea88
Copying 0x1f360 bytes to 0xa05d7e40
Copying 0xde00 bytes to 0xa05f71a0
Copying 0x4728 bytes to 0xa0613480
Setting Lockstep entry point for MCU1 @0x41010000
Copying 0x5c790 bytes to 0x9e800000
Only load (not execute) image @0x9e800000
Copying 0x424d0 bytes to 0x80080000
Only load (not execute) image @0x80080000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0xabc0 bytes to 0x70000000
Setting entry point for core 0 @0x70000000
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 8
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x1...

Second faulty machine:

Unable to successfully handshake with the DDR controller.
Re-updating the DDR parameters did not resolve the issue.
Updating DDR parameters in the e2e link also did not resolve the problem: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1180441/tda4vm-ddr-init-failed-in-sbl

04-ddr-init-error.log

the ok log is:

Fullscreen sbl_ddr_init_ok.log Download

SBL Revision: 01.00.10.01 (Jan 22 2024 - 15:05:30)
TIFS  ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...Board_DDRProbe: PASS
Board_DDRInitDrv: PASS
--->>> LPDDR4 Initialization is in progress ... <<<---
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
--->>> Frequency Change request handshake is completed... <<<---
LPDDR4_Start: PASS
done.
Initializing SERDES ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Searching for X509 certificate ...not found
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x41010000
Copying 0x490 bytes to 0x41010040
Copying 0x448 bytes to 0x410104d0
Copying 0x318 bytes to 0x41010918
Copying 0x118 bytes to 0x41010c30
Copying 0x8c bytes to 0xa0100000
Copying 0x1684 bytes to 0xa058d400
Copying 0x538 bytes to 0xa058ea88
Copying 0x1f360 bytes to 0xa05d7e40
Copying 0xde00 bytes to 0xa05f71a0
Copying 0x4728 bytes to 0xa0613480
Setting Lockstep entry point for MCU1 @0x41010000
Copying 0x5c790 bytes to 0x9e800000
Only load (not execute) image @0x9e800000
Copying 0x424d0 bytes to 0x80080000
Only load (not execute) image @0x80080000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0xabc0 bytes to 0x70000000
Setting entry point for core 0 @0x70000000
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 8
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x1...

We are using the DDR chip Samsung K4FBE3D4HM-THC, and our SDK version is 8.4.

Do you have any directions for troubleshooting this issue?

Best Regards,

Tahm

over 1 year ago

0 Zekun Bai over 1 year ago

TI__Expert 3675 points

Any updates here?

Rgs

Zekun

0 xie jc over 1 year ago in reply to Zekun Bai

Expert 2250 points

Hi, Zekun,

I made some attempts, but it didn't help much so far.

BRs

Tahm

0 Kevin S over 1 year ago in reply to xie jc

TI__Mastermind 38760 points

Hi,

Can you please upload the spreadsheet you used to generate your DDR configuration file?

Regards,
Kevin

0 xie jc over 1 year ago in reply to Kevin S

Expert 2250 points

Hi, Kevin,

Due to some reasons, I cannot find the previous configuration table. the sheet i used to debug is attached below.

SPRACU8B_Jacinto7_DDRSS_RegConfigTool-N50-240219重新配置-startingkernel.rar LP4 32Gb DDP K4FBE3D4HM-TF(H)CL_200F_10x15_1.10.00.pdf

Regards.

Tahm

0 Kevin S over 1 year ago in reply to xie jc

TI__Mastermind 38760 points

Hi Tahm,

Ok no worries. Can you share the DDR header file / DTSI file that you were using in software prior to debug?

In the "OK log", it doesn't look like command bus training is enabled as there are only two frequency changes. Early in TDA4VM development, this was necessary for systems using Samsung dual-rank memory, as CBT was failing when training the second rank. There is now a work-around for this by enabling F0 CA ODT on the IO worksheet tab.

In addition to providing your existing configuration, can you please try the attached configuration?

config_20240221.zip

Regards,
Kevin

0 xie jc over 1 year ago in reply to Kevin S

Expert 2250 points

Hi, Kevin,

Thank you for your response.

The DDR configuration header file we are using is as follows (for production software):

board_ddrRegInit_UsingNow.h

For the DDR configuration table prioritized for debugging purposes, due to the configuration I set up myself recently causing the system to freeze at 'starting kernel,' we will rely on the config_20240221.zip file you provided. Your configuration table works fine on normal boards.

I tried the configuration you provided on both normal and abnormal boards.

Normal board log:

Fullscreen ti_ddr_config240221_OnNormalBoard_20240222_095602.txt Download

SBL Revision: 01.00.10.01 (Feb 22 2024 - 09:51:37)
TIFS  ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ----- new prams from ti..
.Board_DDRProbe: PASS
Board_DDRInitDrv: PASS
--->>> LPDDR4 Initialization is in progress ... <<<---
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 0 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 0 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
--->>> Frequency Change request handshake is completed... <<<---
LPDDR4_Start: PASS
done.
Initializing SERDES ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Searching for X509 certificate ...not found
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x41010000
Copying 0x490 bytes to 0x41010040
Copying 0x448 bytes to 0x410104d0
Copying 0x318 bytes to 0x41010918
Copying 0x118 bytes to 0x41010c30
Copying 0x8c bytes to 0xa0100000
Copying 0x1684 bytes to 0xa058d400
Copying 0x538 bytes to 0xa058ea88
Copying 0x1f360 bytes to 0xa05d7e40
Copying 0xde00 bytes to 0xa05f71a0
Copying 0x4728 bytes to 0xa0613480
Setting Lockstep entry point for MCU1 @0x41010000
Copying 0x5c790 bytes to 0x9e800000
Only load (not execute) image @0x9e800000
Copying 0x424d0 bytes to 0x80080000
Only load (not execute) image @0x80080000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0xabc0 bytes to 0x70000000
Setting entry point for core 0 @0x70000000
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 8
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x1...

Normal board SoC log:

Fullscreen ti_ddr_config240221_OnNormalBoard_20240222_095602_SoC.txt Download

NOTICE:  BL31: v2.6(release):dv-N6X-20231204-7-gac5a1c13f9-dirty
NOTICE:  BL31: Built : 18:45:59, Jan 12 2024
I/TC:
I/TC: OP-TEE version: ac5a1c13f9-dev (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Fri Jan 12 10:46:03 UTC 2024 aarch64
I/TC: Primary CPU initializing
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2021.01 MV: dv-N6X-20231204-7-gac5a1c13f9-dirty (Jan 12 2024 - 18:40:38 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
[spl_boot_device :739] xjc 2: bootmode:16, force to set to BOOT_DEVICE_MMC1
2023-3-22 infor: (boot_device=16)
Trying to boot from MMC2
0x47000004: 0x6
0x47000004: 0x4


U-Boot 2021.01 MV: SOC-master-20240119-dirty (Jan 19 2024 - 10:51:21 +0800), Build: jenkins-Badin_TDA4_BJEV_OS_PreBuild-307

SoC:   J721E SR1.1 GP
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
 bootindex : 1
Loading Environment from FAT... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Hit any key to stop autoboot:  0
 bootindex : 1
Failed to load 'update/u-boot.img'
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
donot Loaded env from uEnv.txt
Running uenvcmd ...
1 bytes read in 10 ms (0 Bytes/s) ->.psdk_setup
Already setup.
8837868 bytes read in 470 ms (17.9 MiB/s) ->/lib/firmware/j7-main-r5f0_0-fw
Load Remote Processor 2 with data@addr=0x82000000 8837868 bytes: Success!
2326852 bytes read in 134 ms (16.6 MiB/s) ->/lib/firmware/j7-main-r5f0_1-fw
Load Remote Processor 3 with data@addr=0x82000000 2326852 bytes: Success!
11846152 bytes read in 625 ms (18.1 MiB/s) ->/lib/firmware/j7-main-r5f1_0-fw
Load Remote Processor 4 with data@addr=0x82000000 11846152 bytes: Success!
Failed to load '/lib/firmware/j7-main-r5f1_1-fw'
8799516 bytes read in 468 ms (17.9 MiB/s) ->/lib/firmware/j7-c66_0-fw
Load Remote Processor 6 with data@addr=0x82000000 8799516 bytes: Success!
8799432 bytes read in 468 ms (17.9 MiB/s) ->/lib/firmware/j7-c66_1-fw
Load Remote Processor 7 with data@addr=0x82000000 8799432 bytes: Success!
20783032 bytes read in 1087 ms (18.2 MiB/s) ->/lib/firmware/j7-c71_0-fw
Load Remote Processor 8 with data@addr=0x82000000 20783032 bytes: Success!
14412288 bytes read in 757 ms (18.2 MiB/s) ->/boot/Image
107206 bytes read in 17 ms (6 MiB/s) ->/boot/k3-j721e-common-proc-board.dtb
13417 bytes read in 12 ms (1.1 MiB/s) ->/boot/k3-j721e-vision-apps.dtbo
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008fee2000, end 000000008fffffff ... OK

Starting kernel ...

I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot

Welcome to Arago 2021.09!

[  OK  ] Created slice system-serial\x2dgetty.slice.
         Starting Journal Service...
         Starting udev Kernel Device Manager...
[  OK  ] Started Journal Service.
         Mounting Kernel Debug File System...
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Reached target System Initialization.
[  OK  ] Reached target Basic System.
         Starting eth.service...
         Starting mit_ota.service...
         Starting run-postinsts.service...
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Started Serial Getty on ttyS3.
[  OK  ] Reached target Login Prompts.
[  OK  ] Started run-postinsts.service.
eth1 sleep 1
eth1 sleep 2
eth1 sleep 3
eth1 sleep 4

SystemDesc:Copyright (c) 2019-2024, Motovis. APA & HPA
GitDesc:9665ec21da master
CompileTime:2024-01-19 11:13:36
eth1 sleep 5
eth1 sleep 6
UpdateInit:1148 exit main process
CreateSocketFd:613 create udp socket sockfd = 4
UpdateInit:1179 3 (0, 1, 254) (0,0,0)
[  OK  ] Started mit_ota.service.
         Starting LSB: Dropbear Secure Shell server...
[  OK  ] Started LSB: Dropbear Secure Shell server.
eth1 sleep 7
eth1 sleep 8
eth1 sleep 9
eth1 sleep 10
eth1 sleep 11
eth1 sleep 12
eth1 sleep 13
eth1 sleep 14
eth1 sleep 15
eth1 sleep 16
eth1 sleep 17
eth1 sleep 18
eth1 sleep 19
eth1 sleep 20
eth1 sleep 21
eth1 sleep 22
eth1 sleep 23
eth1 sleep 24
eth1 sleep 25
eth1 sleep 26
eth1 sleep 27
eth1 sleep 28
eth1 sleep 29
eth1 sleep 30
eth1 sleep 31
eth1 sleep 32
eth1 sleep 33
eth1 sleep 34
eth1 sleep 35
eth1 sleep 36
eth1 sleep 37
eth1 sleep 38
eth1 sleep 39
eth1 sleep 40
eth1 sleep 41
eth1 sleep 42
eth1 sleep 43
eth1 sleep 44
eth1 sleep 45
^Ceth1 sleep 46
eth1 sleep 47
eth1 sleep 48
eth1 sleep 49
eth1 sleep 50
ifconfig: SIOCSIFFLAGS: No such device

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project j7-evm ttyS2

Arago 2021.09 j7-evm ttyS2

j7-evm login:

Abnormal board log1:

Although DDR initialization passed, the SoC gets stuck at BL3x during startup.

Fullscreen ti_ddr_config240221_OnAbonormalBoard03_20240222_095602.txt Download

SBL Revision: 01.00.10.01 (Feb 22 2024 - 09:51:37)
TIFS  ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ----- new prams from ti..
.Board_DDRProbe: PASS
Board_DDRInitDrv: PASS
--->>> LPDDR4 Initialization is in progress ... <<<---
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 0 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 0 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 2 request from Controller
--->>> Frequency Change request handshake is completed... <<<---
LPDDR4_Start: PASS
done.
Initializing SERDES ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Searching for X509 certificate ...not found
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x41010000
Copying 0x490 bytes to 0x41010040
Copying 0x448 bytes to 0x410104d0
Copying 0x318 bytes to 0x41010918
Copying 0x118 bytes to 0x41010c30
Copying 0x8c bytes to 0xa0100000
Copying 0x1684 bytes to 0xa058d400
Copying 0x538 bytes to 0xa058ea88
Copying 0x1f360 bytes to 0xa05d7e40
Copying 0xde00 bytes to 0xa05f71a0
Copying 0x4728 bytes to 0xa0613480
Setting Lockstep entry point for MCU1 @0x41010000
Copying 0x5c790 bytes to 0x9e800000
Only load (not execute) image @0x9e800000
Copying 0x424d0 bytes to 0x80080000
Only load (not execute) image @0x80080000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0xabc0 bytes to 0x70000000
Setting entry point for core 0 @0x70000000
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 8
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
NOTICE:  BL31: v2.6(release):dv-N6X-20231204-7-gac5a1c13f9-dirty
NOTICE:  BL31: Built : 18:45:59, Jan 12 2024

Abnormal board log2:

Stuck at the DDR handshake phase.

Fullscreen ti_ddr_config240221_OnAbonormalBoard04_20240222_095602.txt Download

SBL Revision: 01.00.10.01 (Feb 22 2024 - 09:51:37)
TIFS  ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ----- new prams from ti..
.Board_DDRProbe: PASS
Board_DDRInitDrv: PASS
--->>> LPDDR4 Initialization is in progress ... <<<---
Reg Value: 128
Frequency Change type 1 request from Controller
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Reg

BRs.

Tahm

0 Kevin S over 1 year ago in reply to xie jc

TI__Mastermind 38760 points

Hi Tahm,

Ok, thanks.

On the board that hangs in the DDR handshake phase, can you load and execute the attached binary through Code Composer Studio after the issue occurs? Data should print in the CCS console window. Can you please copy the output data and provide to us for review?

1374.tda4x_lp4_debug.zip

Regards,
Kevin

0 xie jc over 1 year ago in reply to Kevin S

Expert 2250 points

Hi, Kevin,

I loaded tda4vm_lp4_debug.out, but it prompts me that the main function is not defined. Did I make a mistake in my operation?

BRs,

Tahm

0 xie jc over 1 year ago in reply to xie jc

Expert 2250 points

Hi, Kevin,

Any update of this thread?

BRs,

Tahm

0 Kevin S over 1 year ago in reply to xie jc

TI__Mastermind 38760 points

Hi Tahm,

It looks like the binary loaded successfully. You can then select "Run --> Resume" from the CCS menu, or click the F8 button on your keyboard. The output should display in the CCS console window.

Regards,
Kevin

0 xie jc over 1 year ago in reply to Kevin S

Expert 2250 points

Hi, Kevin,

Thanks for your reply.

The output is:

Fullscreen tda4vm-lp4-debug-output-0.txt Download

[MCU_Cortex_R5_0] Training Results; Frequency 0; CS 0
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 680 
	 CA Bit 1 delay: 680 
	 CA Bit 2 delay: 680 
	 CA Bit 3 delay: 680 
	 CA Bit 4 delay: 680 
	 CA Bit 5 delay: 680 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0300
	phy_grp1_slave_delay_0: 0x0300
	phy_grp2_slave_delay_0: 0x0300
	phy_grp3_slave_delay_0: 0x0300
	phy_grp0_slave_delay_1: 0x0300
	phy_grp1_slave_delay_1: 0x0300
	phy_grp2_slave_delay_1: 0x0300
	phy_grp3_slave_delay_1: 0x0300
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 0; CS 1
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 680 
	 CA Bit 1 delay: 680 
	 CA Bit 2 delay: 680 
	 CA Bit 3 delay: 680 
	 CA Bit 4 delay: 680 
	 CA Bit 5 delay: 680 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0300
	phy_grp1_slave_delay_0: 0x0300
	phy_grp2_slave_delay_0: 0x0300
	phy_grp3_slave_delay_0: 0x0300
	phy_grp0_slave_delay_1: 0x0300
	phy_grp1_slave_delay_1: 0x0300
	phy_grp2_slave_delay_1: 0x0300
	phy_grp3_slave_delay_1: 0x0300
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 1; CS 0
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 300 
	 CA Bit 1 delay: 300 
	 CA Bit 2 delay: 300 
	 CA Bit 3 delay: 300 
	 CA Bit 4 delay: 300 
	 CA Bit 5 delay: 300 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0390
	phy_grp1_slave_delay_0: 0x0390
	phy_grp2_slave_delay_0: 0x0390
	phy_grp3_slave_delay_0: 0x0390
	phy_grp0_slave_delay_1: 0x0390
	phy_grp1_slave_delay_1: 0x0390
	phy_grp2_slave_delay_1: 0x0390
	phy_grp3_slave_delay_1: 0x0390
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 1; CS 1
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 300 
	 CA Bit 1 delay: 300 
	 CA Bit 2 delay: 300 
	 CA Bit 3 delay: 300 
	 CA Bit 4 delay: 300 
	 CA Bit 5 delay: 300 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0390
	phy_grp1_slave_delay_0: 0x0390
	phy_grp2_slave_delay_0: 0x0390
	phy_grp3_slave_delay_0: 0x0390
	phy_grp0_slave_delay_1: 0x0390
	phy_grp1_slave_delay_1: 0x0390
	phy_grp2_slave_delay_1: 0x0390
	phy_grp3_slave_delay_1: 0x0390
	phy_top_train_calib_error_info: 0x00000001
DRAM VREF Values:
	mr12_f1_cs0: 0x00000027
	mr12_f1_cs1: 0x00000027
	mr12_f1_cs2: 0x00000027
	mr12_f1_cs3: 0x00000027
	mr12_f2_cs0: 0x00000027
	mr12_f2_cs1: 0x00000027
	mr12_f2_cs2: 0x00000027
	mr12_f2_cs3: 0x00000027
	mr14_f1_cs0: 0x0000000f
	mr14_f1_cs1: 0x0000000f
	mr14_f1_cs2: 0x0000000f
	mr14_f1_cs3: 0x0000000f
	mr14_f2_cs0: 0x0000000f
	mr14_f2_cs1: 0x0000000f
	mr14_f2_cs2: 0x0000000f
	mr14_f2_cs3: 0x0000000f
PHY IO Pad TERM Registers:
	PHY_1320: 0x000146d4
	PHY_1321: 0x000146d4
	PHY_1322: 0x000146d4
	PHY_1323: 0x000146d4
	PHY_1324: 0x000146d4
	PHY_1325: 0x000147d2
	PHY_1326: 0x000147d2
	PHY_1327: 0x000146d4
	PHY_1328: 0x000146d4
Enhanced Error Reporting:
	DQS Gate Error: 0 
	Training Error: 1 
	FSM Tran Error: 0 
	PLL      Error: 0 
	Parity   Error: 0 
	Timeout  Error: 1 
	Timeout Error Info: 
		dfi_rddata_valid           Timeout: 0 
		Max PLL lock assertion     Timeout: 1 
		Min PLL lock assertion     Timeout: 0 
		DFI PHY master interface   Timeout: 0 
		dfi_phyupd_req (PI - PHY)  Timeout: 0 
		dfi_phyupd_req (CTL - PHY) Timeout: 0 
		dfi_lp_ack                 Timeout: 0 
		DFS change @ PI - PHY      Timeout: 0 
		DFS change @ CTL -PHY      Timeout: 1 
		CA / CS training           Timeout: 1 
		WRLVL training             Timeout: 0 
		RDGATE training            Timeout: 0 
		RDDATA training            Timeout: 0 
		WDQ training               Timeout: 0 
	Training Error Info: 0x00000600
	Data Slice Error Info (bits [4:0]): 
		Byte0: 0x00000100
		Byte1: 0x00000100
		Byte2: 0x00000100
		Byte3: 0x00000100
	PLL Frequency Error: 0x0

Fullscreen tda4vm-lp4-debug-output-1.txt Download

[MCU_Cortex_R5_0] Training Results; Frequency 0; CS 0
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 680 
	 CA Bit 1 delay: 680 
	 CA Bit 2 delay: 680 
	 CA Bit 3 delay: 680 
	 CA Bit 4 delay: 680 
	 CA Bit 5 delay: 680 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0300
	phy_grp1_slave_delay_0: 0x0300
	phy_grp2_slave_delay_0: 0x0300
	phy_grp3_slave_delay_0: 0x0300
	phy_grp0_slave_delay_1: 0x0300
	phy_grp1_slave_delay_1: 0x0300
	phy_grp2_slave_delay_1: 0x0300
	phy_grp3_slave_delay_1: 0x0300
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 0; CS 1
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 680 
	 CA Bit 1 delay: 680 
	 CA Bit 2 delay: 680 
	 CA Bit 3 delay: 680 
	 CA Bit 4 delay: 680 
	 CA Bit 5 delay: 680 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0300
	phy_grp1_slave_delay_0: 0x0300
	phy_grp2_slave_delay_0: 0x0300
	phy_grp3_slave_delay_0: 0x0300
	phy_grp0_slave_delay_1: 0x0300
	phy_grp1_slave_delay_1: 0x0300
	phy_grp2_slave_delay_1: 0x0300
	phy_grp3_slave_delay_1: 0x0300
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 1; CS 0
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 300 
	 CA Bit 1 delay: 300 
	 CA Bit 2 delay: 300 
	 CA Bit 3 delay: 300 
	 CA Bit 4 delay: 300 
	 CA Bit 5 delay: 300 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0390
	phy_grp1_slave_delay_0: 0x0390
	phy_grp2_slave_delay_0: 0x0390
	phy_grp3_slave_delay_0: 0x0390
	phy_grp0_slave_delay_1: 0x0390
	phy_grp1_slave_delay_1: 0x0390
	phy_grp2_slave_delay_1: 0x0390
	phy_grp3_slave_delay_1: 0x0390
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 1; CS 1
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 300 
	 CA Bit 1 delay: 300 
	 CA Bit 2 delay: 300 
	 CA Bit 3 delay: 300 
	 CA Bit 4 delay: 300 
	 CA Bit 5 delay: 300 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x008146d4
	CAL_OBS_2: 0x008147d2
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00146d44
	CAL_OBS_5: 0x00147d28
	CAL_OBS_6: 0x00f46d4f
	CAL_OBS_7: 0x03f47d2f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0390
	phy_grp1_slave_delay_0: 0x0390
	phy_grp2_slave_delay_0: 0x0390
	phy_grp3_slave_delay_0: 0x0390
	phy_grp0_slave_delay_1: 0x0390
	phy_grp1_slave_delay_1: 0x0390
	phy_grp2_slave_delay_1: 0x0390
	phy_grp3_slave_delay_1: 0x0390
	phy_top_train_calib_error_info: 0x00000001
DRAM VREF Values:
	mr12_f1_cs0: 0x00000027
	mr12_f1_cs1: 0x00000027
	mr12_f1_cs2: 0x00000027
	mr12_f1_cs3: 0x00000027
	mr12_f2_cs0: 0x00000027
	mr12_f2_cs1: 0x00000027
	mr12_f2_cs2: 0x00000027
	mr12_f2_cs3: 0x00000027
	mr14_f1_cs0: 0x0000000f
	mr14_f1_cs1: 0x0000000f
	mr14_f1_cs2: 0x0000000f
	mr14_f1_cs3: 0x0000000f
	mr14_f2_cs0: 0x0000000f
	mr14_f2_cs1: 0x0000000f
	mr14_f2_cs2: 0x0000000f
	mr14_f2_cs3: 0x0000000f
PHY IO Pad TERM Registers:
	PHY_1320: 0x000146d4
	PHY_1321: 0x000146d4
	PHY_1322: 0x000146d4
	PHY_1323: 0x000146d4
	PHY_1324: 0x000146d4
	PHY_1325: 0x000147d2
	PHY_1326: 0x000147d2
	PHY_1327: 0x000146d4
	PHY_1328: 0x000146d4
Enhanced Error Reporting:
	DQS Gate Error: 0 
	Training Error: 1 
	FSM Tran Error: 0 
	PLL      Error: 0 
	Parity   Error: 0 
	Timeout  Error: 1 
	Timeout Error Info: 
		dfi_rddata_valid           Timeout: 0 
		Max PLL lock assertion     Timeout: 1 
		Min PLL lock assertion     Timeout: 0 
		DFI PHY master interface   Timeout: 0 
		dfi_phyupd_req (PI - PHY)  Timeout: 0 
		dfi_phyupd_req (CTL - PHY) Timeout: 0 
		dfi_lp_ack                 Timeout: 0 
		DFS change @ PI - PHY      Timeout: 0 
		DFS change @ CTL -PHY      Timeout: 1 
		CA / CS training           Timeout: 1 
		WRLVL training             Timeout: 0 
		RDGATE training            Timeout: 0 
		RDDATA training            Timeout: 0 
		WDQ training               Timeout: 0 
	Training Error Info: 0x00000600
	Data Slice Error Info (bits [4:0]): 
		Byte0: 0x00000100
		Byte1: 0x00000100
		Byte2: 0x00000100
		Byte3: 0x00000100
	PLL Frequency Error: 0x0 
Training Results; Frequency 0; CS 0
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 680 
	 CA Bit 1 delay: 680 
	 CA Bit 2 delay: 680 
	 CA Bit 3 delay: 680 
	 CA Bit 4 delay: 680 
	 CA Bit 5 delay: 680 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x00814715
	CAL_OBS_2: 0x00814813
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00147154
	CAL_OBS_5: 0x00148138
	CAL_OBS_6: 0x00f4715f
	CAL_OBS_7: 0x03f4813f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0300
	phy_grp1_slave_delay_0: 0x0300
	phy_grp2_slave_delay_0: 0x0300
	phy_grp3_slave_delay_0: 0x0300
	phy_grp0_slave_delay_1: 0x0300
	phy_grp1_slave_delay_1: 0x0300
	phy_grp2_slave_delay_1: 0x0300
	phy_grp3_slave_delay_1: 0x0300
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 0; CS 1
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 680 
	 CA Bit 1 delay: 680 
	 CA Bit 2 delay: 680 
	 CA Bit 3 delay: 680 
	 CA Bit 4 delay: 680 
	 CA Bit 5 delay: 680 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x00814715
	CAL_OBS_2: 0x00814813
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00147154
	CAL_OBS_5: 0x00148138
	CAL_OBS_6: 0x00f4715f
	CAL_OBS_7: 0x03f4813f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0300
	phy_grp1_slave_delay_0: 0x0300
	phy_grp2_slave_delay_0: 0x0300
	phy_grp3_slave_delay_0: 0x0300
	phy_grp0_slave_delay_1: 0x0300
	phy_grp1_slave_delay_1: 0x0300
	phy_grp2_slave_delay_1: 0x0300
	phy_grp3_slave_delay_1: 0x0300
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 1; CS 0
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 300 
	 CA Bit 1 delay: 300 
	 CA Bit 2 delay: 300 
	 CA Bit 3 delay: 300 
	 CA Bit 4 delay: 300 
	 CA Bit 5 delay: 300 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x00814715
	CAL_OBS_2: 0x00814813
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00147154
	CAL_OBS_5: 0x00148138
	CAL_OBS_6: 0x00f4715f
	CAL_OBS_7: 0x03f4813f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0390
	phy_grp1_slave_delay_0: 0x0390
	phy_grp2_slave_delay_0: 0x0390
	phy_grp3_slave_delay_0: 0x0390
	phy_grp0_slave_delay_1: 0x0390
	phy_grp1_slave_delay_1: 0x0390
	phy_grp2_slave_delay_1: 0x0390
	phy_grp3_slave_delay_1: 0x0390
	phy_top_train_calib_error_info: 0x00000001
Training Results; Frequency 1; CS 1
PHY Vref Training:
	 DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
	 DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
	 ACC Vref Control: 0x7ab 
CA Training:
	 LP4 CA Programmed Delays:
	 CA Bit 0 delay: 300 
	 CA Bit 1 delay: 300 
	 CA Bit 2 delay: 300 
	 CA Bit 3 delay: 300 
	 CA Bit 4 delay: 300 
	 CA Bit 5 delay: 300 
Write Leveling:
	 DQ Lane 0 WRDQS: 0x0 
	 DQ Lane 1 WRDQS: 0x0 
	 DQ Lane 2 WRDQS: 0x0 
	 DQ Lane 3 WRDQS: 0x0 
	 DQ Lane 0 Write Path Latency Add: 0x0 
	 DQ Lane 1 Write Path Latency Add: 0x0 
	 DQ Lane 2 Write Path Latency Add: 0x0 
	 DQ Lane 3 Write Path Latency Add: 0x0 
Gate Training: 
	 DQS Gate Lane 0 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 1 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 2 : slave_delay: 109 lat_adj: 5
	 DQS Gate Lane 3 : slave_delay: 109 lat_adj: 5
Read Leveling:
	read_delay_fall, dq0 : 160
	read_delay_rise, dq0 : 160
	read_delay_fall, dq1 : 160
	read_delay_rise, dq1 : 160
	read_delay_fall, dq2 : 160
	read_delay_rise, dq2 : 160
	read_delay_fall, dq3 : 160
	read_delay_rise, dq3 : 160
	read_delay_fall, dq4 : 160
	read_delay_rise, dq4 : 160
	read_delay_fall, dq5 : 160
	read_delay_rise, dq5 : 160
	read_delay_fall, dq6 : 160
	read_delay_rise, dq6 : 160
	read_delay_fall, dq7 : 160
	read_delay_rise, dq7 : 160
	read_delay_fall, dq8 : 160
	read_delay_rise, dq8 : 160
	read_delay_fall, dq9 : 160
	read_delay_rise, dq9 : 160
	read_delay_fall, dq10 : 160
	read_delay_rise, dq10 : 160
	read_delay_fall, dq11 : 160
	read_delay_rise, dq11 : 160
	read_delay_fall, dq12 : 160
	read_delay_rise, dq12 : 160
	read_delay_fall, dq13 : 160
	read_delay_rise, dq13 : 160
	read_delay_fall, dq14 : 160
	read_delay_rise, dq14 : 160
	read_delay_fall, dq15 : 160
	read_delay_rise, dq15 : 160
	read_delay_fall, dq16 : 160
	read_delay_rise, dq16 : 160
	read_delay_fall, dq17 : 160
	read_delay_rise, dq17 : 160
	read_delay_fall, dq18 : 160
	read_delay_rise, dq18 : 160
	read_delay_fall, dq19 : 160
	read_delay_rise, dq19 : 160
	read_delay_fall, dq20 : 160
	read_delay_rise, dq20 : 160
	read_delay_fall, dq21 : 160
	read_delay_rise, dq21 : 160
	read_delay_fall, dq22 : 160
	read_delay_rise, dq22 : 160
	read_delay_fall, dq23 : 160
	read_delay_rise, dq23 : 160
	read_delay_fall, dq24 : 160
	read_delay_rise, dq24 : 160
	read_delay_fall, dq25 : 160
	read_delay_rise, dq25 : 160
	read_delay_fall, dq26 : 160
	read_delay_rise, dq26 : 160
	read_delay_fall, dq27 : 160
	read_delay_rise, dq27 : 160
	read_delay_fall, dq28 : 160
	read_delay_rise, dq28 : 160
	read_delay_fall, dq29 : 160
	read_delay_rise, dq29 : 160
	read_delay_fall, dq30 : 160
	read_delay_rise, dq30 : 160
	read_delay_fall, dq31 : 160
	read_delay_rise, dq31 : 160
Write DQ Training:
	write_delay, dq0 : 640
	write_delay, dq1 : 640
	write_delay, dq2 : 640
	write_delay, dq3 : 640
	write_delay, dq4 : 640
	write_delay, dq5 : 640
	write_delay, dq6 : 640
	write_delay, dq7 : 640
	write_delay, dq8 : 640
	write_delay, dq9 : 640
	write_delay, dq10 : 640
	write_delay, dq11 : 640
	write_delay, dq12 : 640
	write_delay, dq13 : 640
	write_delay, dq14 : 640
	write_delay, dq15 : 640
	write_delay, dq16 : 640
	write_delay, dq17 : 640
	write_delay, dq18 : 640
	write_delay, dq19 : 640
	write_delay, dq20 : 640
	write_delay, dq21 : 640
	write_delay, dq22 : 640
	write_delay, dq23 : 640
	write_delay, dq24 : 640
	write_delay, dq25 : 640
	write_delay, dq26 : 640
	write_delay, dq27 : 640
	write_delay, dq28 : 640
	write_delay, dq29 : 640
	write_delay, dq30 : 640
	write_delay, dq31 : 640
Calibration Registers:
	CAL_OBS_0: 0x00814715
	CAL_OBS_2: 0x00814813
	CAL_OBS_3: 0xb3000000
	CAL_OBS_4: 0x00147154
	CAL_OBS_5: 0x00148138
	CAL_OBS_6: 0x00f4715f
	CAL_OBS_7: 0x03f4813f
CS Programmed Delays:
	phy_grp0_slave_delay_0: 0x0390
	phy_grp1_slave_delay_0: 0x0390
	phy_grp2_slave_delay_0: 0x0390
	phy_grp3_slave_delay_0: 0x0390
	phy_grp0_slave_delay_1: 0x0390
	phy_grp1_slave_delay_1: 0x0390
	phy_grp2_slave_delay_1: 0x0390
	phy_grp3_slave_delay_1: 0x0390
	phy_top_train_calib_error_info: 0x00000001
DRAM VREF Values:
	mr12_f1_cs0: 0x00000027
	mr12_f1_cs1: 0x00000027
	mr12_f1_cs2: 0x00000027
	mr12_f1_cs3: 0x00000027
	mr12_f2_cs0: 0x00000027
	mr12_f2_cs1: 0x00000027
	mr12_f2_cs2: 0x00000027
	mr12_f2_cs3: 0x00000027
	mr14_f1_cs0: 0x0000000f
	mr14_f1_cs1: 0x0000000f
	mr14_f1_cs2: 0x0000000f
	mr14_f1_cs3: 0x0000000f
	mr14_f2_cs0: 0x0000000f
	mr14_f2_cs1: 0x0000000f
	mr14_f2_cs2: 0x0000000f
	mr14_f2_cs3: 0x0000000f
PHY IO Pad TERM Registers:
	PHY_1320: 0x00014715
	PHY_1321: 0x00014715
	PHY_1322: 0x00014715
	PHY_1323: 0x00014715
	PHY_1324: 0x00014715
	PHY_1325: 0x00014813
	PHY_1326: 0x00014813
	PHY_1327: 0x00014715
	PHY_1328: 0x00014715
Enhanced Error Reporting:
	DQS Gate Error: 0 
	Training Error: 1 
	FSM Tran Error: 0 
	PLL      Error: 0 
	Parity   Error: 0 
	Timeout  Error: 1 
	Timeout Error Info: 
		dfi_rddata_valid           Timeout: 0 
		Max PLL lock assertion     Timeout: 1 
		Min PLL lock assertion     Timeout: 0 
		DFI PHY master interface   Timeout: 0 
		dfi_phyupd_req (PI - PHY)  Timeout: 0 
		dfi_phyupd_req (CTL - PHY) Timeout: 0 
		dfi_lp_ack                 Timeout: 0 
		DFS change @ PI - PHY      Timeout: 0 
		DFS change @ CTL -PHY      Timeout: 1 
		CA / CS training           Timeout: 1 
		WRLVL training             Timeout: 0 
		RDGATE training            Timeout: 0 
		RDDATA training            Timeout: 0 
		WDQ training               Timeout: 0 
	Training Error Info: 0x00000600
	Data Slice Error Info (bits [4:0]): 
		Byte0: 0x00000100
		Byte1: 0x00000100
		Byte2: 0x00000100
		Byte3: 0x00000100
	PLL Frequency Error: 0x0

Regards,

Tahm

0 xie jc over 1 year ago in reply to xie jc

Expert 2250 points

Hi, Kevin,

Any update of this thread?

BRs,

Tahm

0 Zekun Bai over 1 year ago in reply to Kevin S

TI__Expert 3675 points

Hi， Kevin

Do you have any ideas about the output from customer test?

Rgs

Zekun

0 Kevin S over 1 year ago in reply to xie jc

TI__Mastermind 38760 points

Hi Tahm,

Thanks for the update. From the output, it looks like command bus training is failing. However, your original configuration that was provided (used in production) had command bus training disabled, and the same issue (stuck during DDR initialization) occurred. Thus, my assumption is that the issue is not specific to command bus training but something that could impact the DDR interface as a whole. Specifically, voltages, clocks, and reset signals are good starting points. My assumption is maybe there is either a faulty part or poor electrical connection on the board.

A few thoughts for next steps on this device:

Voltages: Checking vdd_core, vdda_0p8_pll_ddr, and vdds_ddr with scope / probe or voltmeter to verify voltage. You could also try to increase the voltage by ~ 50 mV to see if there is any impact.
Clocks: Probe the DDR clock if you have probe access on the PCB. Capture on both working and non-working board.
Reset: Check schematic to see if DDR reset signal is point-to-point or has any other circuitry attached. Probe signal on both working and non-working board. I'd also recommend checking the chip select and clock enable signals.
Additionally, we could try a configuration with reduced DDR frequency to see if the frequency has any impact on the failure. Below I have attached the same configuration as previously provided, but at a slower data rate.

board_ddrRegInit_20240307.h

Another option which you may not want to take yet (but eventually) is to swap the TDA4 device between the non-working board and a working board to see if the failure follows the TDA4 device or the PCB. Then, swap the TDA4 units back to their original board to ensure that the original failure signature is still present.

Regards,
Kevin

0 xie jc over 1 year ago in reply to Kevin S

Expert 2250 points

Hi, Kevin,

Thank you for your support. I tried the configuration you provided for lowering the frequency, but it resulted in "NG" . Where can I adjust the DDR voltage to increase it?

BRs,

Tahm

0 xie jc over 1 year ago in reply to xie jc

Expert 2250 points

Hi, Kevin,

update message: raising the core voltage cannot improve this issue

BRs,

Tahm

0 Biao Li over 1 year ago in reply to xie jc

TI__Expert 6550 points

Hi Tahm,

Are this issue still open?

BR,

Biao

0 Biao Li over 1 year ago in reply to Biao Li

TI__Expert 6550 points

Hi Tahm,

can you pls have a try for attach config?

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/Copy-of-SPRACU8B_5F00_Jacinto7_5F00_DDRSS_5F00_RegConfigTool_2D00_N50_2D00_240429_2D00_from-TI.xlsb

BR,

Biao

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TDA4VM-Q1: DDR init fail in SBL