Deart Expert,
When I ported the SBL to my board, there was a. issue when initializing DDR.
I added some logs and found that there was a dead-loop in the function "static void Board_DDRChangeFreqAck(void)" ,whose file is ti-processor-sdk-rtos-j721e-evm-08_04_00_06\pdk_jacinto_08_04_00_21\packages\ti\board\src\j721e_evm\board_ddr.c. The log is as follows.
How should I do?
IFS ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Board_init Board_DDRStart: cfg=0x400
Efuse xlated: VD 2 to 800 mV (OppVid: 0x37, Slave:0x48, Res:0x0)
Successfully set voltage to 800 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...Board_init Board_DDRStart: cfg=0x4
done.
InitlialzingClocks ...Board_init Board_DDRStart: cfg=0x20
done.
Initlialzing DDR ...Initlialzing DDR======== ...Board_init Board_DDRStart: cfg=0x100
Board_DDRInit: eccEnable=0
Board_DDRProbe: PASS
Board_DDRInit Board_DDRProbe: status=0
Board_DDRInitDrv: PASS
Board_DDRInit Board_DDRInitDrv: status=0
Board_DDRInit Board_DDRHWRegInit: status=0
Board_DDRInit Board_DDRStart: pre status=0
Board_DDRStart: 1>>>
Board_DDRStart: 2>>>
LPDDR4_Start>>>>>>>>>>1
LPDDR4_Start>>>>>>>>>>2 result=0
LPDDR4_Start>>>>>>>>>>3 result=0
LPDDR4_StartSequenceController>>>>>>>>>>1
Board_DDRInfoHandler>>>>>>>1
--->>> LPDDR4 Initialization is in progress ... <<<---
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 0 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 0 request from Controller
Reg Value: 0
Reg Value: 128
Frequency Change type 1 request from Controller
Reg Value: 0
Reg Value: 0
Reg Value: 0
Reg Value: 0
Reg Value: 0
Reg Value: 0
Reg Value: 0
Reg Value: 0
Reg Value: 0
