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66AK2G12:Data Switching Timing(D1,D2,D3) for GPMC Burst Write

Hidekazu
Intellectual 880 points
Other Parts Discussed in Thread: 66AK2G12

Hi,Experts

On page 128 of the datasheet,
It is stated that the data changes from the rising edge of GPMC_CLK to D1, D2, and D3 with a delay of F15.
According to this, it seems correct that the other side (FPGA in our usage) should read data on the falling edge of GPMC_CLK.
<www.ti.com/.../66ak2g12.pdf


On page 1423 of the TRM.
It seems to me that it is correct to change data on the falling edge of GPMC_CLK and read data on the rising edge.
<www.ti.com/.../spruhy8i.pdf

In 66AK2G12, when GPMC Burst Write, does the value of D1, D2, and D3 change with the rising/falling edge of GPMC_CLK?

Best Regards,
Hidekazu

  • 0
    TI__Guru**** 191869 points

    Hello Hidekazu

    Thank you for the query.

    Looks like the GPMC expert is out of office this week.

    I am reassigning the thread. Please expect delay in response.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Intellectual 880 points

    Hi,Sreenivasa

    When will the GPMC experts be back?
    I would like an answer as soon as possible.

    Best Regards,
    Hidekazu

  • 0
    TI__Mastermind 30130 points

    Hi Hidekazu,

    I believe what the F15 and the three notes in the datasheet say is that If GpmcFCLKDivider  is 0 for external clock uses divide-by-1 from internal FCLK, then the first data launches on a positive edge then the remaining data launches on negative edges. Positive edge should be used to latch.

    The first data launches at the beginning of the cycle for non-mux, or at WrDataOnADmuxBus for AD-mux and AAD-mux modes.    
    The second data launches from WrAccessTime + 1
    And subsequent data is spaced apart by PageBurstAccessTime.

    When GpmcFCLKDivider is greater than zero for divide-by-2,3,4 then the data could launch on either edge based on programming of GpmcFCLKDivider, ClkActivationTime, WrDataOnADmuxBus, WrAccessTime, PageBurstAccessTime.

    I'm trying to reproduce this in the lab,
    Below waves show from simulation the first case with GpmcFCLKDivider is 0 for divide-by-1.

    Regards,
    Mark

  • 0 in reply to Mark M
    Intellectual 880 points

    Hi,Mark

    Thank you for repry.

    Can you give us the results of the lab verification?

    Best Regards,
    Hidekazu

  • +1 in reply to Hidekazu
    TI__Mastermind 30130 points

    Hi Hidekazu,

    My apologies for the delay. I ran into two road blocks trying to take this data in the lab. Those road blocks are now cleared and I expect to have a result by next week. Just letting you know I havent forgotten you.

    Regards,
    Mark

  • +1 in reply to Mark M
    TI__Mastermind 30130 points

    Hi Hidekazu,

    The lab testing is finally complete. Thank you for your patience.

    Confirmed behavior is below.

    * In div-by-1 mode (GPMCFCLKDIVIDER = 0), first data is always launched on pos edge. Following data (not first) is launched on neg edge. Device shall latch all data on rise edge.

    * In not div-by-1 mode (GPMCFCLKDIVIDER != 0), the GPMC config bitfields have control over which edge is used to launch data.
     - in AD-mux mode, first data is launched at WRDATAONADMUXBUS. WRDATAONADMUXBUS can be a rise or fall GPMC_CLK edge with different values for CLKACTIVATIONTIME.
     - following data (not first) can also be launched on pos or neg edge with different values of CLKACTIVATIONTIME however, TI provides rules for synchronous modes. Following these rules results in data launching on neg edge. Following the rules, the Device shall latch all data on rise edge.

    * GPMC synch rules can be found at https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1186148/faq-tips-for-configuring-sitara-gpmc-registers
    These are the rules that force following data (not first) launches to occur on neg edge:
    - (WRCYCLETIME - CLKACTIVATIONTIME) a multiple of (GPMCFCLKDIVIDER + 1)
    - Sync Write: Rule 2. (WRCYCLETIME – CLKACTIVATIONTIME) must be a multiple of GPMCFCLKDIVIDER+1
    - Sync Write: Rule 3. (WRACCESSTIME – CLKACTIVATIONTIME) modulus (GPMCFCLKDIVIDER + 1) must be different from GPMCFCLKDIVIDER

    Other parameters involved in determining the edge that data is launched are...
    GPMCFCLKDIVIDER, PAGEBURSTACCESSTIME, WRACCESSTIME
    - it is important that PAGEBURSTACCESSTIME corresponds to the GPMCFCLKDIVIDER selection (PAGEBURSTACCESSTIME  = GPMCFCLKDIVIDER + 1)

    * It is worth mentioning also that with non-mux mode the first data is launched at the beginning of the GPMC write cycle. First clock edge launches at CLKACTIVATIONTIME. With CLKACTIVATIONTIME = 0, first data launches on pos edge. With CLKACTIVATIONTIME > 0, first data launches before pos edge.

    I hope this clarifies the behavior and F15 descriptions in the datasheet.

    Regards,
    Mark