PROCESSOR-SDK-J721E: BIST function

Dengkuan Sun

Hi TI Expert.

I am designing our functional safety system based on J721E. I read the information about BIST function and find an example in MCUSW.

For my case, I used MCU1_0 as boot core, MCU1_1 as one safety channel, and one A72 as another safety channel. I learned that only BIST for MCU1_0 was started automatically and other cores (including MCU1_1 and Main Domian) need to be triggered by SW. Therefore, I refered to the example in MCUSW. But, I still have some questions.

In bist.c, what does "PBIST negative test" mean? Also, why to be wrong when "testResult !=0"? Pls refer to the picture.
What is the difference between "PBIST negative test" and "PBIST functional test"?
For the test result, can it be read by stage cores?
For my case, because MCU1_0 is not functional safety channel, if MCU1_0 calls SDL to do BIST for MCU1_1 and A72, can it be ensured as the safety result to use?

Thanks

Dengkuan

over 1 year ago

0 Josiitaa RL over 1 year ago

TI__Mastermind 41446 points

Hi Dengkuan,

The SDL BIST documentation can be referenced by the following links:

1. testResult = 0 or SDL_PASS is considered the pass condition in the code sequence. Hence testResult !=0 returns a failure.

2. Negative testing ensures the system works as expected under error conditions. The Safety Manual has diagnostics for Software Test of PBIST, for example: A72SS.RAM-T2 - Software Test of PBIST, "where it is possible to configure the PBIST logic by selecting an algorithm that should fail and seeing if the PBIST Logic reports an error under this condition".

Whereas the Auto-coverage diagnostic mentioned in the safety manual measures are based on the probability of a random failure causing PBIST to falsely pass a test. The PBIST check of memory diagnostic provides a reliable way to identify stuck-at/permanent faults in the memory. Both these cases are taken care of by the functional test.

'SDL_PBIST_TEST' takes care of normal scenario and 'SDL_PBIST_NEG_TEST' injects error and verify that module is able to detect errors in a desired way.

3. I do not understand what you mean by reading stage cores here. Could you clarify?

4. The Main R5F's and A72 should be tested as early as possible in the boot flow, before they are in use. The PBIST must be run on a different core, than the core that is being tested. Yes, the MCU R5 would be a good location to run PBIST on Main R5F0/1 and A72.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

Pls refer to my comments:

1. From your code, the testResult is added "1". Therefore, failure case results to testRsult as 0.

3. In this example, MCU1_0 triggers the BIST test of other cores and reads the test result. I mean whether the tested core reads the test result after MCU1_0 triggers the BIST test of the tested core and boots it.

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi Dengkuan,

Dengkuan Sun said:
1. From your code, the testResult is added "1". Therefore, failure case results to testRsult as 0.

Please note that the pbist_pre_boot_stage_neg_status[i] has the value of testResult +1 (0 - fail; 1 - pass). The value of testResult remains the same (-1 - fail; 0 - pass).

Dengkuan Sun said:
In this example, MCU1_0 triggers the BIST test of other cores and reads the test result. I mean whether the tested core reads the test result after MCU1_0 triggers the BIST test of the tested core and boots it.

Yes, it is possible to check the test result by reading the status registers of the PBIST controller of each core.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Thanks.

Another question, for boot_app_mcu_rtos in sdk 09_00_00_02, can it run on j784? I found whether some files are missed by comparing SOC\j721e and SOC\j784s4. Pls refer to the following picture.

Also, can you help me to find which file to show the registers which can be read to show the BIST results for different cores?

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

For J784S4, the idea is to move to the BootApp in the PDK directory, to provide a more scalable solution. The MCUSW BootApp is therefore currently not validated. However, we are still in the process of including BIST to the PDK BootApp. You should see it in one of the upcoming releases.

You can however use the patches below to include BIST to the PDK BootApp (the patches have been test on SDK 9.1, but the same approach can be followed for 9.0 as well) -

Fullscreen 2475.0001-SBL-Boot-PDK-Boot-Application.txt Download

From 7be4cdb3861a7145099c4c0be940242276eaed46 Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Thu, 25 Jan 2024 13:59:58 +0530
Subject: [PATCH] SBL Boot + PDK Boot Application

---
 packages/ti/boot/sbl/board/k3/sbl_main.c      | 321 +++++++++++++++++-
 packages/ti/boot/sbl/build/boot_app.mk        |  42 ++-
 packages/ti/boot/sbl/build/sbl_img.mk         |  47 +++
 .../boot/sbl/example/boot_app/boot_app_main.c |  39 +++
 packages/ti/boot/sbl/sbl_component.mk         |   1 +
 .../src/rm_pm_hal/pm/soc/j784s4/dmsc.c        |   5 +
 6 files changed, 448 insertions(+), 7 deletions(-)

diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c
index 82a5177..854a2bf 100755
--- a/packages/ti/boot/sbl/board/k3/sbl_main.c
+++ b/packages/ti/boot/sbl/board/k3/sbl_main.c
@@ -43,6 +43,22 @@
 #include "sbl_main.h"
 #include <ti/csl/cslr_gtc.h>
 #include <sbl_err_trap.h>
+#if defined (SBL_ENABLE_BIST)
+#include <bist.h>
+#include <pbist_utils.h>
+#include <sdl_pbist.h>
+#include <bist_core_defs.h>
+#include <test/osal/osal_interface.h>
+#if defined(SOC_J721E)
+#include <ti/board/src/j721e_evm/include/board_utils.h>
+#elif defined(SOC_J7200)
+#include <ti/board/src/j7200_evm/include/board_utils.h>
+#elif defined(SOC_J721S2)
+#include <ti/board/src/j721s2_evm/include/board_utils.h>
+#elif defined(SOC_J784S4)
+#include <ti/board/src/j784s4_evm/include/board_utils.h>
+#endif
+#endif
 
 /**********************************************************************
  ************************** Macros ************************************
@@ -65,6 +81,52 @@ volatile uint32_t *sblProfileLogIndxAddr __attribute__((section(".sbl_profile_in
 
 volatile uint32_t *sblProfileLogOvrFlwAddr __attribute__((section(".sbl_profile_info")));
 
+#if defined (SBL_ENABLE_BIST)
+#define KICK0_UNLOCK               (0x68EF3490U)
+#define KICK1_UNLOCK               (0xD172BC5AU)
+
+#define PLL0_LOCKKEY0                                  (0x00680010U)
+#define PLL0_LOCKKEY1                                  (0x00680014U)
+#define PLL1_LOCKKEY0                                  (0x00681010U)
+#define PLL1_LOCKKEY1                                  (0x00681014U)
+#define PLL2_LOCKKEY0                                  (0x00682010U)
+#define PLL2_LOCKKEY1                                  (0x00682014U)
+#define PLL3_LOCKKEY0                                  (0x00683010U)
+#define PLL3_LOCKKEY1                                  (0x00683014U)
+#define PLL4_LOCKKEY0                                  (0x00684010U)
+#define PLL4_LOCKKEY1                                  (0x00684014U)
+#define PLL5_LOCKKEY0                                  (0x00685010U)
+#define PLL5_LOCKKEY1                                  (0x00685014U)
+#define PLL6_LOCKKEY0                                  (0x00686010U)
+#define PLL6_LOCKKEY1                                  (0x00686014U)
+#define PLL7_LOCKKEY0                                  (0x00687010U)
+#define PLL7_LOCKKEY1                                  (0x00687014U)
+#define PLL8_LOCKKEY0                                  (0x00688010U)
+#define PLL8_LOCKKEY1                                  (0x00688014U)
+#define PLL9_LOCKKEY0                                  (0x00689010U)
+#define PLL9_LOCKKEY1                                  (0x00689014U)
+#define PLL12_LOCKKEY0                                 (0x0068C010U)
+#define PLL12_LOCKKEY1                                 (0x0068C014U)
+#define PLL14_LOCKKEY0                                 (0x0068E010U)
+#define PLL14_LOCKKEY1                                 (0x0068E014U)
+#define PLL16_LOCKKEY0                                 (0x00690010U)
+#define PLL16_LOCKKEY1                                 (0x00690014U)
+#define PLL17_LOCKKEY0                                 (0x00691010U)
+#define PLL17_LOCKKEY1                                 (0x00691014U)
+#define PLL19_LOCKKEY0                                 (0x00693010U)
+#define PLL19_LOCKKEY1                                 (0x00693014U)
+#define PLL25_LOCKKEY0                                 (0x00699010U)
+#define PLL25_LOCKKEY1                                 (0x00699014U)
+#define PLL26_LOCKKEY0                                 (0x0069A010U)
+#define PLL26_LOCKKEY1                                 (0x0069A014U)
+#if defined(SOC_J784S4)
+#define PLL27_LOCKKEY0                                 (0x0069B010U)
+#define PLL27_LOCKKEY1                                 (0x0069B014U)
+#define PLL28_LOCKKEY0                                 (0x0069C010U)
+#define PLL28_LOCKKEY1                                 (0x0069C014U)
+#endif
+#endif
+
 sblEntryPoint_t k3xx_evmEntry;
 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
 {
@@ -245,6 +307,199 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
 
 };
 
+#if defined (SBL_ENABLE_BIST)
+
+void SBL_unlockPllMmrs(void)
+{
+    HW_WR_REG32(PLL0_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL0_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL1_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL1_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL2_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL2_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL3_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL3_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL4_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL4_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL5_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL5_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL6_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL6_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL7_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL7_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL8_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL8_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL12_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL12_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL14_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL14_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL16_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL16_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL17_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL17_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL19_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL19_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL25_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL25_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL26_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL26_LOCKKEY1, KICK1_UNLOCK);
+#if defined (SOC_J784S4)
+    HW_WR_REG32(PLL27_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL27_LOCKKEY1, KICK1_UNLOCK);
+    HW_WR_REG32(PLL28_LOCKKEY0, KICK0_UNLOCK);
+    HW_WR_REG32(PLL28_LOCKKEY1, KICK1_UNLOCK);
+#endif
+}
+
+
+static void MainDomainBootSetup(void)
+{
+    int32_t retVal;
+    Sciclient_DefaultBoardCfgInfo_t boardCfgInfo;
+
+    /* Unlock PLL MMRs putting back to same state prior to reset */
+    SBL_log(SBL_LOG_MAX, "Unlocking pll mmrs ...");
+    SBL_unlockPllMmrs();
+    SBL_log(SBL_LOG_MAX, "done.\n");
+
+    Sciclient_BoardCfgPrms_t bootAppBoardCfgPrms = {
+                                                    .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLow,
+                                                    .boardConfigHigh = 0,
+                                                    .boardConfigSize = boardCfgInfo.boardCfgLowSize,
+                                                    .devGrp = DEVGRP_01
+                                                   };
+    Sciclient_BoardCfgPrms_t bootAppBoardCfgPmPrms = {
+                                                      .boardConfigLow = (uint32_t)NULL,
+                                                      .boardConfigHigh = 0,
+                                                      .boardConfigSize = 0,
+                                                      .devGrp = DEVGRP_01
+                                                     };
+    Sciclient_BoardCfgPrms_t bootAppBoardCfgRmPrms = {
+                                                      .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowRm, 
+                                                      .boardConfigHigh = 0,
+                                                      .boardConfigSize = boardCfgInfo.boardCfgLowRmSize,
+                                                      .devGrp = DEVGRP_01
+                                                     };
+    Sciclient_BoardCfgPrms_t bootAppBoardCfgSecPrms = {
+                                                       .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowSec,
+                                                       .boardConfigHigh = 0,
+                                                       .boardConfigSize = boardCfgInfo.boardCfgLowSecSize,
+                                                       .devGrp = DEVGRP_01
+                                                      };
+    retVal = Sciclient_boardCfg(&bootAppBoardCfgPrms);
+    if (retVal != CSL_PASS)
+    {
+         SBL_log(SBL_LOG_MAX,"Sciclient_boardCfg() failed.\n");
+    }
+    retVal = Sciclient_boardCfgPm(&bootAppBoardCfgPmPrms);
+    if (retVal != CSL_PASS)
+    {
+         SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgPm() failed.\n");
+    }
+    retVal = Sciclient_boardCfgRm(&bootAppBoardCfgRmPrms);
+    if (retVal != CSL_PASS)
+    {
+         SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgRm() failed.\n");
+    }
+    retVal = Sciclient_boardCfgSec(&bootAppBoardCfgSecPrms);
+    if (retVal != CSL_PASS)
+    {
+         SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgSec() failed.\n");
+    }
+    /* Init Pinmux */
+    if(Board_init(BOARD_INIT_PINMUX_CONFIG) != BOARD_SOK)
+	{
+       SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_PINMUX_CONFIG\n");
+	}
+	/* Init PLLS */
+    Board_init(BOARD_INIT_PLL_MAIN);
+
+
+	/* Init Clocks */
+    Board_initParams_t initParams;
+    Board_getInitParams(&initParams);
+    initParams.mainClkGrp = BOARD_MAIN_CLOCK_GROUP1;
+    initParams.mcuClkGrp  = BOARD_MCU_CLOCK_GROUP1;
+    Board_setInitParams(&initParams);
+    if(Board_init(BOARD_INIT_MODULE_CLOCK_MAIN) != BOARD_SOK)
+	{
+       SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_MODULE_CLOCK\n");
+	}
+	
+	/* Unlock CTRL MMR */
+	SBL_log(SBL_LOG_MAX, "Unlocking CTRL MMRs ...");
+    if(Board_init(BOARD_INIT_UNLOCK_MMR) != BOARD_SOK)
+	{
+       SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_UNLOCK_MMR\n");
+	}
+    SBL_log(SBL_LOG_MAX, "done.\n");
+}
+
+#endif
+
+/* Refer TISCI_MSG_SYS_RESET in TISCI user guide for more details
+   http://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/sysreset.html */
+int32_t SBL_swResetMainDomain(void)
+{
+    int32_t retVal = E_FAIL;
+
+    struct tisci_msg_sys_reset_req request;
+    struct tisci_msg_sys_reset_resp response = {0};
+
+    Sciclient_ReqPrm_t reqParam = {0};
+    Sciclient_RespPrm_t respParam = {0};
+
+    memset(&request, 0, sizeof(request));
+    request.domain = 0x2; /* 0x2 corresponds to the MAIN domain */
+
+    reqParam.messageType    = (uint16_t) TISCI_MSG_SYS_RESET;
+    reqParam.flags          = (uint32_t) TISCI_MSG_FLAG_AOP;
+    reqParam.pReqPayload    = (const uint8_t *) &request;
+    reqParam.reqPayloadSize = (uint32_t) sizeof (request);
+    reqParam.timeout        = (uint32_t) SCICLIENT_SERVICE_WAIT_FOREVER;
+    respParam.flags           = (uint32_t) 0;   /* Populated by the API */
+    respParam.pRespPayload    = (uint8_t *) &response;
+    respParam.respPayloadSize = (uint32_t) sizeof (response);
+
+    retVal = Sciclient_service(&reqParam, &respParam);
+    if (((respParam.flags & TISCI_MSG_FLAG_ACK) == 0) || (retVal != CSL_PASS))  {
+        SBL_log(SBL_LOG_ERR,"SBL_swResetMainDomain failed, retVal = %d\n resp flag = 0x%08x\n",
+                     retVal, respParam.flags);
+    }
+
+    return retVal;
+}
+
+void SBL_runPBIST(uint32_t instanceId, bool runNegTest)
+{
+    int32_t testResult = 0;
+
+
+    if(runNegTest)
+	{
+        /* Run test on provided instance */
+        testResult = PBIST_runTest(instanceId, true);
+        /* PBIST_runtTest return value (-1 = failure and 0 = pass) */
+        if ( testResult != 0)
+        {
+            SBL_log(SBL_LOG_ERR,"PBIST negative test failed for %d\n",
+                            instanceId);
+        }
+    }
+	else
+	{
+        /* Run test on provided instance */
+        testResult = PBIST_runTest(instanceId, false);
+        /* PBIST_runtTest return value (-1 = failure and 0 = pass) */
+        if ( testResult != 0)
+        {
+            SBL_log(SBL_LOG_ERR,"PBIST functional test failed for %d\n",
+                            instanceId);
+        }
+    }
+}
+
+volatile uint32_t loopSwResetMainDomain = 0xDEADBEEF;
 int main()
 {
     int32_t retVal = CSL_PASS;
@@ -359,7 +614,7 @@ int main()
 
 #if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
     SBL_ADD_PROFILE_POINT;
-    SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
+    SBL_log(SBL_LOG_MAX, "Initializing PLLs ...");
     if (CSL_PASS != Board_init(SBL_PLL_INIT))
     {
         retVal = CSL_EFAIL;
@@ -384,12 +639,64 @@ int main()
 #endif
 #endif
     SBL_ADD_PROFILE_POINT;
-    if (CSL_PASS != Board_init(SBL_CLOCK_INIT))
+    if(Board_init(SBL_CLOCK_INIT) != BOARD_SOK)
+	{
+       SBL_log(SBL_LOG_ERR,"Board_init failed for SBL_CLOCK_INIT\n");
+	   retVal = CSL_EFAIL;
+	}
+    SBL_log(SBL_LOG_MAX, "done.\n");
+#endif
+
+#if defined (SBL_ENABLE_BIST)
+#if 0
+    /* For debug purpose */
+    if(loopSwResetMainDomain == 0xDEADBEEF)
     {
-        retVal = CSL_EFAIL;
-        SBL_log(SBL_LOG_ERR, "\n Failed to initialize clocks !! \n");
+        SBL_log(SBL_LOG_MAX, "Connect CCS and change loopSwResetMainDomain to 0!\n");
+        SBL_log(SBL_LOG_MAX, "After that the MAIN domain will be reset!\n");
+    }
+    while(loopSwResetMainDomain == 0xDEADBEEF);
+#endif
+
+    /* Initialize SDL Osal Layer */
+    int32_t ret = SDL_TEST_osalInit();
+    if (ret != SDL_PASS)
+    {
+        SBL_log(SBL_LOG_MAX,"Error: Init Failed\n");
     }
 
+    /* PBIST MAININFRA_1 Negative / Positive */
+    SBL_runPBIST(PBIST_INSTANCE_MAININFRA_1, true);
+    SBL_runPBIST(PBIST_INSTANCE_MAININFRA_1, false);
+
+    /* PBIST MAININFRA_0 Negative / Positive */
+    SBL_runPBIST(PBIST_INSTANCE_MAININFRA_0, true);
+    SBL_runPBIST(PBIST_INSTANCE_MAININFRA_0, false);
+
+    /* PBIST MSMC  Negative / Positive */
+    SBL_runPBIST(PBIST_INSTANCE_MSMC, true);
+    SBL_runPBIST(PBIST_INSTANCE_MSMC, false);
+
+    /* PBIST NAVSS Negative / Positive */
+    SBL_runPBIST(PBIST_INSTANCE_NAVSS, true);
+    SBL_runPBIST(PBIST_INSTANCE_NAVSS, false);
+
+    /* PBIST HC Negative / Positive */
+    SBL_runPBIST(PBIST_INSTANCE_HC, true);
+    SBL_runPBIST(PBIST_INSTANCE_HC, false);
+
+    /* PBIST CODEC1 Negative / Positive */
+    //SBL_runPBIST(PBIST_INSTANCE_CODEC_1, true);
+    //SBL_runPBIST(PBIST_INSTANCE_CODEC_1, false);
+
+    /* Reset Main Domain */
+    SBL_log(SBL_LOG_MAX, "Resetting Main Domain ...");
+    SBL_swResetMainDomain();
+    SBL_log(SBL_LOG_MAX, "done.\n");
+
+    /* Recover Main Domain */
+    SBL_log(SBL_LOG_MAX, "Recovering Main Domain ...");
+    MainDomainBootSetup();
     SBL_log(SBL_LOG_MAX, "done.\n");
 #endif
 
@@ -400,7 +707,7 @@ int main()
         retVal = CSL_EFAIL;
         SBL_log(SBL_LOG_ERR, "\n Failed to initialize DDR !! \n");
     }
-    SBL_log(SBL_LOG_MAX, "done.\n");
+	SBL_log(SBL_LOG_MAX, "done.\n");
 #endif
 
 #if defined(SBL_ENABLE_SERDES)
@@ -418,12 +725,14 @@ int main()
     SBL_log(SBL_LOG_MAX, "Initializing GTC ...");
     volatile uint32_t *gtcRegister = (uint32_t *) CSL_GTC0_GTC_CFG1_BASE;
     *gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK;
-
+    SBL_log(SBL_LOG_MAX, "done.\n");
 #if defined(SOC_J721E) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J7200)) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J784S4))
+#if !defined (SBL_ENABLE_BIST)
     /* Configure external Ethernet PHY and pinmux */
     SBL_ConfigureEthernet();
 #endif
 #endif
+#endif
 
 #if !defined(BOOT_PERF)
     SBL_log(SBL_LOG_MAX, "Copying EEPROM content to DDR ... \n");
diff --git a/packages/ti/boot/sbl/build/boot_app.mk b/packages/ti/boot/sbl/build/boot_app.mk
index c17ccb9..0cbacef 100644
--- a/packages/ti/boot/sbl/build/boot_app.mk
+++ b/packages/ti/boot/sbl/build/boot_app.mk
@@ -64,6 +64,46 @@ ifeq ($(HLOSBOOT), linux)
 else ifeq ($(HLOSBOOT), qnx)
     CFLAGS_LOCAL_COMMON += -DMPU1_HLOS_BOOT_ENABLED -DHLOS_BOOT_QNX_OS
 endif
+ifeq ($(HLOSBOOT), linux)
+    CFLAGS_LOCAL_COMMON += -DBIST_TASK_ENABLED
+    #CFLAGS_LOCAL_COMMON += 
+	
+    # SDL Include Files
+    SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl
+    INCDIR += $(SDL_INSTALL_PATH)/
+    INCDIR += $(SDL_INSTALL_PATH)/osal/
+    INCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+    INCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+    INCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+    INCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+    INCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)/
+    INCDIR += $(SDL_INSTALL_PATH)/src/sdl
+    INCDIR += $(SDL_INSTALL_PATH)/test/osal/
+    INCDIR += $(SDL_INSTALL_PATH)/src/ip
+    INCDIR += $(SDL_INSTALL_PATH)/include
+    INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC)
+
+    # SDL Source File Paths
+    SRCDIR += $(SDL_INSTALL_PATH)/osal/
+    SRCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+    SRCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+    SRCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+    SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+    SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+    SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src
+
+    # SDL Integration
+    EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/osal/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_osal.$(LIBEXT)
+    EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_ip.$(LIBEXT)
+    EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/sdl/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_api.$(LIBEXT)
+    EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/r5/lib/$(SOC)/r5f/$(BUILD_PROFILE)/r5f_core.$(LIBEXT)
+
+    SRCS_COMMON += osal_interface.c
+    SRCS_COMMON += bist.c bist_core_defs.c
+    SRCS_COMMON += lbist_utils.c lbist_defs.c
+    SRCS_COMMON += pbist_utils.c pbist_defs.c
+    SRCS_COMMON += power_seq.c armv8_power_utils.c
+endif
 
 EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/boot_app/linker_r5_freertos.lds
 
@@ -73,4 +113,4 @@ ifeq ($(MAKERULEDIR), )
   MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
   export MAKERULEDIR
 endif
-include $(MAKERULEDIR)/common.mk
\ No newline at end of file
+include $(MAKERULEDIR)/common.mk
diff --git a/packages/ti/boot/sbl/build/sbl_img.mk b/packages/ti/boot/sbl/build/sbl_img.mk
index 11d2d34..0e48059 100644
--- a/packages/ti/boot/sbl/build/sbl_img.mk
+++ b/packages/ti/boot/sbl/build/sbl_img.mk
@@ -111,6 +111,53 @@ else ifeq ($(BOOTMODE), xip)
     SBL_CFLAGS += -DOSPI_FREQ_166
   endif
   COMP_LIST_COMMON += sbl_lib_cust$(HS_SUFFIX)
+else ifeq ($(BOOTMODE), mmcsd)
+  #SBL_CFLAGS = $(CUST_SBL_FLAGS)
+  # Uncomment to enable PBIST functionality in SBL
+  SBL_CFLAGS += -DSBL_ENABLE_BIST
+  SUPRESS_WARNINGS_FLAG += -Wno-unused-but-set-variable
+
+
+  COMP_LIST_COMMON += sbl_lib_$(BOOTMODE)$(HS_SUFFIX)
+
+  # SDL Include Files
+  SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl
+  INCDIR += $(SDL_INSTALL_PATH)/
+  INCDIR += $(SDL_INSTALL_PATH)/osal/
+  INCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+  INCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+  INCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+  INCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+  INCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)/
+  INCDIR += $(SDL_INSTALL_PATH)/test/osal/
+  INCDIR += $(SDL_INSTALL_PATH)/test/pbist/$(SOC)/
+  INCDIR += $(SDL_INSTALL_PATH)/test/pbist/pbist_sdl/
+  INCDIR += $(SDL_INSTALL_PATH)/src/sdl
+  INCDIR += $(SDL_INSTALL_PATH)/src/ip
+  INCDIR += $(SDL_INSTALL_PATH)/include
+  INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC)
+
+  # SDL Source File Paths
+  SRCDIR += $(SDL_INSTALL_PATH)/osal/
+  SRCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+  SRCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+  SRCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+  SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+  SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+  SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src
+
+
+  # SDL Integration
+  EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/osal/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_osal.$(LIBEXT)
+  EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_ip.$(LIBEXT)
+  EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/sdl/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_api.$(LIBEXT)
+  EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/r5/lib/$(SOC)/r5f/$(BUILD_PROFILE)/r5f_core.$(LIBEXT)
+
+  SRCS_COMMON += osal_interface.c
+  SRCS_COMMON += bist.c bist_core_defs.c
+  SRCS_COMMON += lbist_utils.c lbist_defs.c
+  SRCS_COMMON += pbist_utils.c pbist_defs.c
+  SRCS_COMMON += power_seq.c armv8_power_utils.c
 else
   COMP_LIST_COMMON += sbl_lib_$(BOOTMODE)$(DMA_SUFFIX)$(HLOS_SUFFIX)$(HS_SUFFIX)
 endif # ifeq ($(BOOTMODE), cust)
diff --git a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
index 4c0c499..c48c109 100644
--- a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
+++ b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
@@ -81,6 +81,10 @@
 #elif defined(BOOT_OSPI)
 #include "boot_app_ospi.h"
 #endif
+#if defined(BIST_TASK_ENABLED)
+#include "bist.h"
+#include "test/osal/osal_interface.h"
+#endif
 
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
@@ -91,6 +95,10 @@
 /**< Task Priority Levels */
 #define BOOT_TASK_PRIORITY              (2)
 
+#if defined(BIST_TASK_ENABLED)
+#define BIST_TASK_PRIORITY   (3)
+#define BIST_TASK_STACKSIZE  (10U * 1024U)
+#endif 
 /* uncomment the following for debug logs */
 // #define UART_PRINT_DEBUG
 
@@ -125,6 +133,12 @@ static uint8_t gBootAppTaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
 TaskP_Handle gbootTask;
 static uint64_t gtimeBootAppStart, gtimeBootAppFinish;
 
+#if defined(BIST_TASK_ENABLED)
+//static uint8_t Bist_TaskStack[BIST_TASK_STACKSIZE] __attribute__((aligned(32)));
+TaskP_Handle gbistTask;
+static uint64_t gtimeBistAppStart, gtimeBistAppFinish;
+#endif
+
 int32_t main(void)
 {
     Board_initCfg boardCfg;
@@ -177,6 +191,22 @@ static void BootApp_TaskFxn(void* a0, void* a1)
     return;
 }
 
+
+#if defined(BIST_TASK_ENABLED)
+static void BistApp_TaskFxn(void* a0, void* a1)
+{
+    gtimeBistAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+    bist_TaskFxn();
+
+    gtimeBistAppFinish = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+    UART_printf("\nMCU Bist Task started at %d usecs and finished at %d usecs\r\n", (uint32_t)gtimeBistAppStart, (uint32_t)gtimeBistAppFinish);
+
+    return;
+}
+#endif
+
 uint32_t Boot_App()
 {
     uint32_t       retVal;
@@ -205,6 +235,15 @@ uint32_t Boot_App()
     }
 #endif
 
+#if defined(BIST_TASK_ENABLED)
+
+    /* Initialize the SDL osal */
+    SDL_TEST_osalInit();
+
+	/* Start the Bist Task */
+    BistApp_TaskFxn(NULL, NULL)  ;
+#endif
+
     /* Initialize the entry point array to 0. */
     for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
         (&gK3xx_evmEntry)->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk
index 2477c72..76c9a16 100644
--- a/packages/ti/boot/sbl/sbl_component.mk
+++ b/packages/ti/boot/sbl/sbl_component.mk
@@ -1350,6 +1350,7 @@ SBL_CFLAGS += -DSBL_LOG_LEVEL=2
 SBL_CFLAGS += -DSBL_ENABLE_PLL
 SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
 SBL_CFLAGS += -DSBL_ENABLE_DDR
+SBL_CFLAGS += -DSBL_ENABLE_BIST
 
 ifeq ($(SOC), $(filter $(SOC), j721e))
 SBL_CFLAGS += -DSBL_ENABLE_SERDES
diff --git a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c
index 748a295..739399f 100644
--- a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c
+++ b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c
@@ -95,6 +95,11 @@ static s32 wait_reset_done_with_timeout(domgrp_t domain)
 	if (timeout == 0U) {
 		ret = -ETIMEDOUT;
 	}
+	else
+	{
+	    /* Delay to allow access Main domain */
+        osal_delay(250);
+	}
 
 	return ret;
 }
-- 
2.34.1

Fullscreen 0827.0001-SDL-Changes-to-integrate-to-BootApp.txt Download

From 8041d4a6bbc8f7ca983fce247562faa8c90df577 Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Thu, 25 Jan 2024 14:01:26 +0530
Subject: [PATCH] SDL Changes to integrate to BootApp

---
 examples/bist/bist.c                  | 78 ++++++++++++++++++++++++++-
 examples/bist/pbist_utils.c           |  9 ++--
 examples/bist/soc/j784s4/pbist_defs.c | 16 +++++-
 3 files changed, 95 insertions(+), 8 deletions(-)

diff --git a/examples/bist/bist.c b/examples/bist/bist.c
index 09a9b43..ef89c66 100644
--- a/examples/bist/bist.c
+++ b/examples/bist/bist.c
@@ -87,7 +87,7 @@
 /* ========================================================================== */
 
 /* This flag adds more verbose prints */
-//#define DEBUG
+/*#define DEBUG*/
 
 /* This flags enables gathering timing information for BIST stages */
 #define GATHER_BIST_STAGE_DETAILS
@@ -295,6 +295,31 @@ void bist_TaskFxn(void)
 				{
 					continue;
 				}
+				/* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */
+                if((i==7)|| (i==2)||(i==6)||(i==25))
+				{
+					continue;
+				}
+				/* HC has MMCSD in Auxiallary list, run this in SBL */
+				if(i==9)
+				{
+					continue;
+				}
+                /* TODO: Codecs are impacting QNX SDMMC driver */
+                if ((i==12) || (i==1))
+                {
+                    continue;
+				}
+                /* TODO: DSS is impacting QNX SDMMC driver */
+                if (i==4)
+                {
+                    continue;
+                }
+                /* TODO: Debugging issue with A72s PBIST, do not run */
+                if ((i==13)|| (i==14)||(i==15)||(i==16))
+                {
+                    continue;
+                }
                 #endif		
                 /*MCU instances are not supported for neg and pos test, 
                 So skipped according to the pbist_first_boot_stage array sequence */				
@@ -350,6 +375,31 @@ void bist_TaskFxn(void)
 				{
 					continue;
 				}
+                /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */
+                if((i==7)|| (i==2)||(i==6)||(i==25))
+                {
+                    continue;
+                }
+                /* HC has MMCSD in Auxiallary list, run this in SBL */
+                if(i==9)
+                {
+                    continue;
+                }
+                /* TODO: Codecs are impacting QNX SDMMC driver */
+                if ((i==12)  || (i==1))
+                {
+                    continue;
+				}
+                /* TODO: DSS is impacting QNX SDMMC driver */
+                if (i==4)
+                {
+                    continue;
+                }
+                /* TODO: Debugging issue with A72s PBIST, do not run */
+                if ((i==13)|| (i==14)||(i==15)||(i==16))
+                {
+                    continue;
+                }
                 #endif	
                 /*MCU instances are not supported for neg and pos test, 
                 So skipped according to the pbist_first_boot_stage array sequence */					
@@ -395,6 +445,32 @@ void bist_TaskFxn(void)
             #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)
             for (i = 0; i < num_pbists_per_boot_stage[j]; i++)
             {
+
+                /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */
+                if((i==7)|| (i==2)||(i==6)||(i==25))
+                {
+                    continue;
+                }
+                /* HC has MMCSD in Auxiallary list, run this in SBL */
+                if(i==9)
+                {
+                    continue;
+                }
+                /* TODO: Codecs are impacting QNX SDMMC driver */
+                if ((i==12) || (i==1))
+                {
+                    continue;
+				}
+                /* TODO: DSS is impacting QNX SDMMC driver */
+                if (i==4)
+                {
+                    continue;
+                }
+                /* TODO: Debugging issue with A72s PBIST, do not run */
+                if ((i==13)|| (i==14)||(i==15)||(i==16))
+                {
+                    continue;
+                }
                 /* Run test on selected instance */
                 testResult = PBIST_runTest(pbist_array[i], (uint8_t)PBIST_TEST_ROM);
 
diff --git a/examples/bist/pbist_utils.c b/examples/bist/pbist_utils.c
index ea8e5e1..f5e81da 100644
--- a/examples/bist/pbist_utils.c
+++ b/examples/bist/pbist_utils.c
@@ -535,14 +535,13 @@ int32_t PBIST_commonInit(void)
 {
  #if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4)
     CSL_ErrType_t status;
-    int32_t retValue = 0;
+
     /* Add firewall entry to gain access to CLEC registers */
     status = PBIST_setFirewall();
 
     if (status != CSL_PASS)
     {
         UART_printf( " PBIST_setFirewall failed \n");
-        retValue = -1;
     }
 
     return status;
@@ -1384,7 +1383,7 @@ int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
             UART_printf("  Secondary core: Taking out of local reset the core %s \n",
                         PBIST_TestHandleArray[instanceId].secCoreName);
 #endif
-            status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecProcId,
+            status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
                                               0x0, /* Local Reset de-asserted */
                                               SCICLIENT_SERVICE_WAIT_FOREVER);
             if (status != CSL_PASS)
@@ -1403,7 +1402,7 @@ int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
         UART_printf("  Third core: Taking out of local reset the core %s \n",
                     PBIST_TestHandleArray[instanceId].thCoreName);
 #endif
-        status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThProcId,
+        status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
                                           0x0, /* Local Reset de-asserted */
                                           SCICLIENT_SERVICE_WAIT_FOREVER);
         if (status != SDL_PASS)
@@ -1422,7 +1421,7 @@ int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
         UART_printf("  Third core: Taking out of local reset the core %s \n",
                     PBIST_TestHandleArray[instanceId].foCoreName);
 #endif
-        status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoProcId,
+        status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
                                           0x0, /* Local Reset de-asserted */
                                           SCICLIENT_SERVICE_WAIT_FOREVER);
         if (status != SDL_PASS)
diff --git a/examples/bist/soc/j784s4/pbist_defs.c b/examples/bist/soc/j784s4/pbist_defs.c
index cd08934..fbed6b1 100755
--- a/examples/bist/soc/j784s4/pbist_defs.c
+++ b/examples/bist/soc/j784s4/pbist_defs.c
@@ -103,7 +103,7 @@
 
 #define MAIN_R5F1_NUM_AUX_DEVICES         4
 
-#define MAIN_INFRA1_NUM_AUX_DEVICES       6
+#define MAIN_INFRA1_NUM_AUX_DEVICES       18
 
 #define HC_NUM_AUX_DEVICES                12
 
@@ -194,6 +194,18 @@ uint32_t PBIST_MainInfra1AuxDevList[MAIN_INFRA1_NUM_AUX_DEVICES] =
     TISCI_DEV_MCAN3,
     TISCI_DEV_MCAN4,
     TISCI_DEV_MCAN5,
+    TISCI_DEV_MCAN6,
+    TISCI_DEV_MCAN7,
+    TISCI_DEV_MCAN8,
+    TISCI_DEV_MCAN9,
+    TISCI_DEV_MCAN10,
+    TISCI_DEV_MCAN11,
+    TISCI_DEV_MCAN12,
+    TISCI_DEV_MCAN13,
+    TISCI_DEV_MCAN14,
+    TISCI_DEV_MCAN15,
+    TISCI_DEV_MCAN16,
+    TISCI_DEV_MCAN17
 };
 
 uint32_t PBIST_HCAuxDevList[HC_NUM_AUX_DEVICES] =
@@ -1423,4 +1435,4 @@ void PBIST_printPostStatus(SDL_PBIST_postResult *result)
     UART_printf("    HW POST MCU Status : %s\n", (PBIST_getPostStatusString(result->mcuPostStatus)) ? : "Invalid");
 
     return;
-}
\ No newline at end of file
+}
-- 
2.34.1

Dengkuan Sun said:
can you help me to find which file to show the registers which can be read to show the BIST results for different cores?

You can refer to the sdl_ip_pbist.c source code present in PSDKR/SDL/src/ip/pbist/V0

The Fail Status Fail Register (FSFR) is expected to be all zeros if PBIST passes successfuly. You can find the value of PBISTRegs for each instance in the sdl_soc_pbist.c file in SDL/src/sdl/pbist/soc/j721e directory.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

Can you help to confirm whether sdl\example\bist in ti-processor-sdk-rtos-j784s4-evm-09_01_00_06 can work if I would like to use it as a j784s4 demo? If no, can you help me to give more instrument how to fix some error?

Thanks

Dengkuan

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi Dengkuan,

The standalone SDL BIST example does work as expected on J784S4. Is that what you are looking for? Or are you looking to combine it with a Boot application?

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Thanks Josiitaa,

Currently, I want to look for a demo only for verifying the BIST function of different cores. Therefore, based on your suggetion, I can transplant the code into my project for verifying the BIST. Is that correctly?

For my next step, I will based on the bist flow to add my BOOT application.

In addition, for SDK 08_08_00_14, does sdl\example\bist work for j784s4?

Thanks

Dengkuan

0 Dengkuan Sun over 1 year ago in reply to Dengkuan Sun

Prodigy 240 points

Josiitaa,

Today, I built sdl\example\bist in ti-processor-sdk-rtos-j784s4-evm-08_06_00_14 into my demo. But the result is shown as fail.

Can you give some suggestion?

Thanks

Dengkuan

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Could you refer to this FAQ and implement the steps given? - (+) [FAQ] TDA4VM: SDL BIST Example Application Failing on SDK 8.6 - Processors forum - Processors - TI E2E support forums

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Thanks for answering so quickly.

I checked the answer. For the first step, I cannot use git to download the code. But I can download the sdk from TI websit. I can compare all of files under bist example between sdk 8.6 and sdk 9.0 or 9.1, and change them based on sdk 9.0 or sdk 9.1. For the second step, because I transplated the bist example code into my project without booting other cores, and the code is run MCU1_0 in mcu domain. So, it is impossible to use multiple core image. Do you have any suggestion about this?

In addition, I checked the instance. Does "SDL_LBIST_HWPOST_INST_MCU" include MCU1_0 and MCU1_1? If not, where to define it?

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Are you using SDK 8.6 or 9.0? Starting SDK 9.1, you would not need the multicore image. SDK 8.6 and 9.0, the MCU R5 is by default in non-secure mode and can no longer modify the CLEC. PBIST tests to run they require that the CLEC be programmed from the MCU R5. So, a C7x image has been created to allow for clearing of the "secure claim bit" to allow MCU R5 to access CLEC.

Dengkuan Sun said:
Does "SDL_LBIST_HWPOST_INST_MCU" include MCU1_0 and MCU1_1? If not, where to define it?

POST runs on all MCU R5 memories.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Sorry for the confusion.

Let me explain more detail.

For the bist example based on SDK 8.6, I try to transplant it my application because the current system is developed based on sdk 8.6. From your suggestion and my understand, I try to fix the bug by comparing the code between SDK 8.6 and SDK 9.1 and merging them. But it seems not to work. Is it possible to send the whole code which can work on SDK 8.6 to me?

For the bist example based on SDK 9.1, I try to verify it based on j784s4 EVM board. When I try to build it and run by the command "gmake -s bist_example_app SOC=j784s4 CORE=r5f PROFILE=debug BUILD_OS=freertos", it shows the following error:

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Josiitaa RL said:

Could you refer to this FAQ and implement the steps given? - (+) [FAQ] TDA4VM: SDL BIST Example Application Failing on SDK 8.6 - Processors forum - Processors - TI E2E support forums

For running the BIST standalone example on SDK 8.6, you would have to use the patch in this FAQ.

Dengkuan Sun said:
For the bist example based on SDK 9.1, I try to verify it based on j784s4 EVM board. When I try to build it and run by the command "gmake -s bist_example_app SOC=j784s4 CORE=r5f PROFILE=debug BUILD_OS=freertos", it shows the following error:

Are you using Windows? We only validate the SDL examples on Linux, so I am not sure of the extent of support we can offer on Windows. I will however look into it and see if I can find some issue.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Josiitaa,

I am using Windows.

Josiitaa RL said:
Could you refer to this FAQ and implement the steps given? - (+) [FAQ] TDA4VM: SDL BIST Example Application Failing on SDK 8.6 - Processors forum - Processors - TI E2E support forums

For running the BIST standalone example on SDK 8.6, you would have to use the patch in this FAQ.

Except using git, how can I download the patch?

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Dengkuan Sun said:
I am using Windows.

It is suggested to build SDL on Linux as we do not build tests on Windows. We strongly recommend that you move to Linux as we run regular build tests on Linux and Linux is a lot faster as well.

Dengkuan Sun said:
Except using git, how can I download the patch?

You can manually include the changes to your code without git.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Josiitaa RL said:
Dengkuan Sun said:
Except using git, how can I download the patch?

You can manually include the changes to your code without git.

Does that mean that I will deleted the code with "-" and add the codes with "+" in the file which was attached to your suggested method.? Also, it can be built and tested based on Windows.

Josiitaa RL said:
Dengkuan Sun said:
I am using Windows.

It is suggested to build SDL on Linux as we do not build tests on Windows. We strongly recommend that you move to Linux as we run regular build tests on Linux and Linux is a lot faster as well.

But, our system is based on Windows to develop. Pls help to fix this.

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Dengkuan Sun said:
Does that mean that I will deleted the code with "-" and add the codes with "+" in the file which was attached to your suggested method.?

Yes, that is correct.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

Whether to verify the compiler of window version for SDK9.1?

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Dengkuan Sun said:
Whether to verify the compiler of window version for SDK9.1?

Im sorry, I do not understand your question here.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Dengkuan Sun

Prodigy 240 points

Hi Josiitaa,

I am trying to use your patch to fix the bug based on sdk 8.6. But, I have some configuration.

Dengkuan Sun said:
Could you refer to this FAQ and implement the steps given? - (+) [FAQ] TDA4VM: SDL BIST Example Application Failing on SDK 8.6 - Processors forum - Processors - TI E2E support forums

This is for J721E not for J784s4.

I tried to use this which you suggested. But, I cannot find what to be changed for j78s4. Can you attach a whole project so that I can refer?

Based on my schedule, it is urgent to fix this. Pls response this.

Thanks

Dengkuan

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Josiitaa RL said:
Dengkuan Sun said:
Whether to verify the compiler of window version for SDK9.1?

Im sorry, I do not understand your question here.

You said that you would verify BIST example for SDK 9.1 based on Windows. I would like to know the result. I also want to know how to fix my compiling error which I attached here before. I attched here again.

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

We do not support windows testing, but I am trying to reproduce the issue. I will get back to you by EOD today.

Regards,

Josiitaa

0 Josiitaa RL over 1 year ago in reply to Josiitaa RL

TI__Mastermind 41446 points

Hi,

There are 2 MulticoreImageGen in /ti-processor-sdk-rtos-j784s4-evm-09_01_00_06/pdk_j784s4_09_01_00_22/packages/ti/boot/sbl/tools/multicoreImageGen. You should use the MulticoreImageGen.exe instead of MulticoreImageGen. That is what seems to be the issue. Since we do not test on Windows, I am unable validate this fix.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Josiitaa,

Josiitaa RL said:
There are 2 MulticoreImageGen in /ti-processor-sdk-rtos-j784s4-evm-09_01_00_06/pdk_j784s4_09_01_00_22/packages/ti/boot/sbl/tools/multicoreImageGen. You should use the MulticoreImageGen.exe instead of MulticoreImageGen

How should I do this change?

Dengkuan Sun said:
Hi Josiitaa,

I am trying to use your patch to fix the bug based on sdk 8.6. But, I have some configuration.

Dengkuan Sun said:
Could you refer to this FAQ and implement the steps given? - (+) [FAQ] TDA4VM: SDL BIST Example Application Failing on SDK 8.6 - Processors forum - Processors - TI E2E support forums

This is for J721E not for J784s4.

I tried to use this which you suggested. But, I cannot find what to be changed for j78s4. Can you attach a whole project so that I can refer?

Based on my schedule, it is urgent to fix this. Pls response this.

Thanks

Dengkuan

Pls give your feedback about this BY EOD TODAY.

Thanks

Dengkuan

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Dengkuan Sun said:
How should I do this change?

Include the highlighted section of code in SDL/build/makerules/common.mk

Dengkuan Sun said:
I tried to use this which you suggested. But, I cannot find what to be changed for j78s4. Can you attach a whole project so that I can refer?

I am trying to reproduce your failure on my side so I can generate the patch. Could you share your error logs for this case?

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

pls refer to this.

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

I have tested the standalone SDL bist_example application on SDK 8.6 for J784s4 TI EVM (without including FAQ changes) and I do not see this failure. Are there any other applications running or some other change in your setup?

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

I just transplated the whole code into my application. Also, they are run before other functions.

In addition, because I have only J721E EVM board, I followed your instructions which we discussed before to build the bist example based on J721e SDK 09_01_00_06 and test the image based on J721E EVM. After it shows the following information "Boot stage 0 is complete, cores for this stage may now be loaded", the code is blocked. Therefore, I am very confused.

So, can you give the detail instructions like the following items based on Windows Enviroment:

Based on J721E EVM, can you list all the detail instructions so that I can follow your suggestions for step by step to build and download it into EVM based on CCS.
Based on my application and J784S4, can you list all the detail instructions so that I can transplate the code into my applicaiton for verify the bist function. My requirement is the bist test of MCU1_1 and A72 is triggered and tested by MCU1_0, and the bist result is read by MCU1_0 and A72.

Thanks

Dengkuan

0 Keerthy J over 1 year ago in reply to Dengkuan Sun

TI__Guru**** 163170 points

Hello,

Dengkuan Sun said:
So, can you give the detail instructions like the following items based on Windows Enviroment:

We do not support SDL for windows. We have not validated on windows. So kindly request you to use Linux/ubuntu for the SDL related features.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/09_01_00_06/exports/docs/psdk_rtos/docs/user_guide/getting_started_j721e.html

SDL is not in the windows supported list.

Regards,
Keerthy

0 Dengkuan Sun over 1 year ago in reply to Keerthy J

Prodigy 240 points

I switched to Ubuntu in VMware and built the bist_example_app based on J721E SDK 09_01_00_06. It shows the following error:

# /home/sdkuan/Downloads/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/sdl/binary/bist_example_app/bin/j721e/bist_example_app_r5f_baremetal_debug.xer5f created.
#
/bin/sh: 1: mono: not found
make[1]: *** [/home/sdkuan/Downloads/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/sdl/build/makerules/common.mk:304: sbl_appimagerprc] Error 127
make: *** [makefile:144: bist_example_app] Error 2

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Mono is required for building the SDK on linux. You can check if mono is installed by typing “mono –version” at the linux prompt. If mono is not installed, download and install mono from this link - Home | Mono (mono-project.com)

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

For next step, can I use the CCS 12.9 to download the image into J721E EVM board to verify the result? Or, what will I need to take care any steps?

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Please refer to this userguide to run applications on CCS - 6. CCS Setup for J721E — Processor SDK RTOS J721E (ti.com)

The other ways of booting the EVM to run examples are mentioned here - 5. EVM Setup for J721E — Processor SDK RTOS J721E (ti.com)

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

I verify the bist_example_app by ccs 12.2 loading based on Ubuntu 22.4. The result seems to be the same with one based on Windows. I attached debug informaiton here.

[MCU_Cortex_R5_0] SCICLIENT_CCS_INIT: Oct 17 2023, 13:53:00Sciclient_Init Passed.
=================================================================
DEVGRP = 1
=================================================================
SYSFW Common Board Configuration with Debug enabled... PASSED
SYSFW PM Board Configuration... PASSED
SYSFW Security Board Configuration... PASSED
=================================================================
Sciclient Dev Group 01 initilization started
Power on the WKUPMCU to MAIN and MAIN to WKUPMCU VDs... PASSED
=================================================================
DEVGRP = 2
=================================================================
SYSFW Common Board Configuration with Debug enabled... PASSED
SYSFW PM Board Configuration... PASSED
SYSFW Security Board Configuration... PASSED
=================================================================
DMSC Firmware Version 9.1.2--v09.01.02 (Kool Koala)
Firmware revision 0x9
ABI revision 3.1
=================================================================
Sciclient_ccs_init Passed.
SCISERVER Board Configuration header population... PASSED

Starting PBIST failure insertion test on PBIST HWPOST MCU, index 0...

Starting PBIST failure insertion test on Main Infra PBIST, index 12...

Starting PBIST failure insertion test on MSMC PBIST, index 13...

Starting PBIST test on PBIST HWPOST MCU, index 0...

Starting PBIST test on Main Infra PBIST, index 12...

Starting PBIST test on MSMC PBIST, index 13...

Starting PBIST failure insertion test on Main R5F 0 PBIST, index 2...

Starting PBIST test on Main R5F 0 PBIST, index 2...

*** Boot stage 0 is complete, cores for this stage may now be loaded ***

Starting PBIST failure insertion test on Main R5F 1 PBIST, index 3...

Starting PBIST failure insertion test on C7X PBIST, index 4...

Starting PBIST failure insertion test on C6x core 0 PBIST, index 10...

Starting PBIST failure insertion test on C6x core 1 PBIST, index 11...

Starting PBIST failure insertion test on VPAC PBIST, index 6...

Starting PBIST failure insertion test on DMPAC PBIST, index 7...

Starting PBIST failure insertion test on A72 PBIST, index 5...

Starting PBIST failure insertion test on HC PBIST, index 9...

Starting PBIST failure insertion test on Encoder PBIST, index 14...

Starting PBIST failure insertion test on Decoder PBIST, index 15...

Starting PBIST test on Main R5F 1 PBIST, index 3...

Starting PBIST test on C7X PBIST, index 4...

Starting PBIST test on C6x core 0 PBIST, index 10...

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Which SDK are you testing on? If its the SDK 8.6 or 9.0, you will have to load the C7x binary as well.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

I am testing 9.1.

In addition, can you list the detail steps for SDK 8.6, 9.0 and 9.1 so that I can follow them to repeat the correct result? I am so sad for so many days not to solve the problem.

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Can you try booting using MMCSD boot mode? I have tried executing both 8.6, 9.0 and 9.1 SDK for J721E and it works successfully.

Below are the steps to load applications via MMCSD boot mode:

Build the bist_example_app using the build command make bist_example_app in SDL/
Copy the bist_example_app_r5f_baremetal_multicore_image.appimage (for SDK 8.6 and 9.0) and bist_example_app_r5f_baremetal_debug.appimage (for SDK 9.1) into the SD card as app
Copy PDK/packages/ti/boot/sbl/binary/j721e_evm/mmcsd/bin/sbl_mmcsd_img_mcu1_0_release.tiimage into the SD card as tiboot3.bin
Copy PDK/packages/ti/drv/sciclient/soc/V1/tifs.bin into the SD card as tifs.bin
Set the boot mode pins on the EVM as per image below. Insert SD card and boot.

You should see the logs on the MCU UART on USB terminal 1.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Josiitaa,

I followed your instructions to test bist_example based on building sdk 9.1. It cannot work.

sd files

UART information

Also, I would like to know what the difference between CCS downloading and SD is. If I transplant the code to my application that MCU1_0 starts BIST test of MCU1_1 and A72, and MC1_1 and A72 read the result the bist result when they finished themselves, how to do this?

URGENT TO FINISH THE TEST AND APPLICATION!!

Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Dengkuan Sun said:
UART information

This looks like Linux logs from the MAIN UART. Please try with just the 3 images I mentioned in the SD card and connect the USB cable to the MCU UART not the MAIN UART.

Dengkuan Sun said:
Also, I would like to know what the difference between CCS downloading and SD is.

We do not validate SDL examples on CCS. Hence I am trying to identify if you are seeing the issue on SD/UART boot mode.

Dengkuan Sun said:
If I transplant the code to my application that MCU1_0 starts BIST test of MCU1_1 and A72, and MC1_1 and A72 read the result the bist result when they finished themselves, how to do this?

Josiitaa RL said:
The Fail Status Fail Register (FSFR) is expected to be all zeros if PBIST passes successfuly. You can find the value of PBISTRegs for each instance in the sdl_soc_pbist.c file in SDL/src/sdl/pbist/soc/j721e directory.

As mentioned in my previous reply, you have to verify that the values of the FSFR are zeros, to check the PBIST result from a different core.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Good news for me. I can use SD to run the demo.

Josiitaa RL said:
Dengkuan Sun said:
Also, I would like to know what the difference between CCS downloading and SD is.

We do not validate SDL examples on CCS. Hence I am trying to identify if you are seeing the issue on SD/UART boot mode.

Before using SD to test the demo, I used CCS to download the demo into MCU1_0. But, it cannot work. This is why to ask how to use CCS to test the demo. Maybe, I did some wrong steps. Can you list the detail steps about how to run the demo by CCS downloading like SD mode steps?

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

That is great to hear.

We do not validate on CCS so TI is unable to support directly loading the program on CCS.

If you are looking to debug using CCS, you can follow the below steps -

Add breakpoints (while loops) in the code and rebuild and run using SD mode as mentioned above. It will halt at the breakpoint.
Connect the JTAG cable to the EVM.
Launch Target configuration for J721E on CCS.
Connect target on MCU_Cortex_R5_0.
Load the symbols of the bist_example_app on MCU_Cortex_R5_0.

You can then step through and debug.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

I will try to run the bist_example in MCU1_0 and code some codes to read the bist test results based on MCU1_1 based on SD. Can you help to list the steps how I can build the image and how to copy them to SD to run my case.

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

If you are modifying the SDL bist example, you can use the same steps as mentioned in my previous response.

Josiitaa RL said:
Below are the steps to load applications via MMCSD boot mode:

Build the bist_example_app using the build command make bist_example_app in SDL/

Copy the bist_example_app_r5f_baremetal_multicore_image.appimage (for SDK 8.6 and 9.0) and bist_example_app_r5f_baremetal_debug.appimage (for SDK 9.1) into the SD card as app

Copy PDK/packages/ti/boot/sbl/binary/j721e_evm/mmcsd/bin/sbl_mmcsd_img_mcu1_0_release.tiimage into the SD card as tiboot3.bin

Copy PDK/packages/ti/drv/sciclient/soc/V1/tifs.bin into the SD card as tifs.bin

Set the boot mode pins on the EVM as per image below. Insert SD card and boot.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Josiitaa,

I would like to build a demo by following the steps which is describled as the following figure:

For my case, stage 1 is used to boot MCU1_1 which will read the its bist result by MCU1_0 done, and stage 2 is used to boot A72 which will read the its bist result by MCU1_0 done. Therefore, my questions are listed as the following:

How can I build the multiimage? Are they multi-app or only one app?pls list the detail steps like your image steps.
How can I set up a SD image to run the demo and see the printed information? Does it follow your suggested steps?

Thanks

Dengkuan

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Please refer to this link 5.3. Boot App to build the PDK Boot application, which can boot the cores. You can modify the cores in each stage in the boot_core_defs.c file present in PDK/packages/ti/boot/sbl/example/boot_app/soc/j721e/

Once that is running successfuly, you will have to include BIST Apis from SDL into the boot application to test BIST. Currently the Boot application is not integrated with BIST. The system integrator will have to do that.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

I checked the steps in 5.3. Boot App. I still have some questions about this. Therefore, I listed the steps which I would like to do my demo based on my understanding:

I build the images: MCU1_0 image----BIST_example, MCU1_1 image------the code which is used to call the bist apis to read its bist result, A72 image----the code which is used to call the bist apis to read its bist result. Also, MCU1_0 image is stage 1, MCU1_1 is stage 2, and A72 image is stage 3. And I need to change the name by following generate_lateapps.sh like "
multicore_MCU1_0_MCU1_0_stage1.appimage, multicore_MCU1_0_MCU1_1_stage2.appimage, multicore_MPU1__stage3.appimage"
Change boot_core_defs.c for the demo
Follow the steps in 5.3. Boot App to set up the SD card

Pls check my steps and correct them.

In addition, I copy the 5.3. Boot App here. For these steps, pls check my questions: (sdk J721E 09_01_00_06)

Booting lateapps via MMCSD

Generate lateapps by using the following commands

goto <PDK>/packages/ti/boot/sbl/example/boot_app/scripts

Run ./make_multicore_appimages.sh <board_name> there is only generate_lateapps.sh in the scripts folder. Therefore, this step should run ./generate_lateapps.sh <j721e_evm>? Also, I should change some context based on my demo like the following figure？
When I tried to run this command, it shows the error "gcc-arm compiler not found. Please refer user guide to download the same"

Multicore images(lateapps) will be generated in <PDK>/packages/ti/boot/sbl/example/boot_app/multicore_images/$BOARD/.

Stage1 image corresponds to lateapp1, stage2 image corresponds to lateapp2 and stage3 image corresponds to lateapp3.

Copy sbl_mmcsd_img_mcu1_0_release.tiimage as tiboot3.bin to the boot partition of SD card

Copy tifs.bin to the boot partition of SD card

Build boot_app_mmcsd by using the following command

make BOARD=<board_name> CORE=mcu1_0 boot_app_mmcsd -sj

Copy sbl_boot_app_mmcsd_<board_name>_mcu1_0_freertos_TestApp_release.appimage image as app to the boot partition of SD card

Copy stage1 image as lateapp1, stage2 image as lateapp2 and stage3 image as lateapp3 to the boot partition of SD card Does that mean changing multicore_MCU1_0_MCU1_0_stage1.appimage to lateapp1?

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

Please follow these steps to boot to A72 Linux via SD card:

Generate lateapps by using the following commands

goto <RTOS SDK>/<PDK>/packages/ti/boot/sbl/example/boot_app/scripts

Run ./generate_lateapps.sh j721e_evm

Multicore images(lateapps) will be generated in <PDK>/packages/ti/boot/sbl/example/boot_app/multicore_images/j721e_evm/.

multicore_MCU2_0_MCU2_1_stage1.appimage corresponds to lateapp1, multicore_DSPs_MCU3_0_MCU3_1_MCU4_0_MCU4_1_stage2.appimage corresponds to lateapp2 and multicore_MPU1_0_stage3.appimage corresponds to lateapp3.

Copy sbl_mmcsd_img_mcu1_0_release.tiimage present in <PDK>/packages/ti/boot/sbl/binary/j721e_evm/mmcsd/bin as tiboot3.bin to the boot partition of SD card

Copy tifs.bin present in <PDK>/packages/ti/drv/sciclient/soc/V6 to the boot partition of SD card.

goto <RTOS SDK>/<PDK>/packages/ti/build and build boot_app_mmcsd_linux by using the following command:

make BOARD=j784s4_evm CORE=mcu1_0 boot_app_mmcsd_linux -sj

Copy sbl_boot_app_mmcsd_linux_j721e_evm_mcu1_0_freertos_TestApp_release.appimage present in <PDK>/packages/ti/boot/sbl/example/boot_app/binary/j721e_evm/mmcsd as app to the boot partition of SD card.

Copy stage1 image as lateapp1, stage2 image as lateapp2 and stage3 image as lateapp3 to the boot partition of SD card.

Copy atf_optee.appimage, tidtb_linux.appimage, tikernelimage_linux.appimage present in<PDK>/packages/ti/boot/sbl/tools/BootApp_binaries/linux/j721e_evm to the boot partition of SD card.

Boot the board using this SD card on MMCSD boot mode, and you should see the SBL Logs on MCU_UART and the Linux logs on the MAIN_UART.

Dengkuan Sun said:
Also, I should change some context based on my demo like the following figure？

You can change the names of the appimages based on your usecase.

Dengkuan Sun said:
When I tried to run this command, it shows the error "gcc-arm compiler not found. Please refer user guide to download the same"

You will have to install this compiler in the RTOS SDK folder from this link - Downloads | GNU-A Downloads – Arm Developer

Dengkuan Sun said:
Does that mean changing multicore_MCU1_0_MCU1_0_stage1.appimage to lateapp1?

Yes.

Regards,

Josiitaa

0 Dengkuan Sun over 1 year ago in reply to Josiitaa RL

Prodigy 240 points

Hi Josiitaa,

I tried to transplate the BIST function into boo app. But there are a lot of bugs which need to be fixed. Therefore, it is impossible to set up a demo for my application very quickly. I found that the demo "boot_app_mcu_rtos in mcuss_demos based on SDK 721E 09_01_00_06" is a best option to implement my thought. Therefore, I built it without mpu1_0, c66 and c7x and follow the steps to set up sd to run the demo. But it failed. Can you help me to give some suggestions to run the demo? Thanks

0 Josiitaa RL over 1 year ago in reply to Dengkuan Sun

TI__Mastermind 41446 points

Hi,

The MCUSW Bootapp is currently not validated with BIST integrated. We have sample patches to integrate BIST with the PDK boot application that is tested on SKD 9.1. I can share those with you, if required, so you can refer to it and perform a similar integration on J721E.

Regards,

Josiitaa