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Original question:

AM623: Transfer rate of CBASS

AM623: Internal bus

Kanae
Guru 10085 points
Part Number: AM623

Jianzhong and Support Team,


I have confirmed that the bus width between MIPI CSI-2 and CABSS is 128 bits at the following
but will you disclose the internal buses of other peripherals?
Could you please describe them clearly in the TRM?

e2e.ti.com/.../

Best Regards,
Kanae

  • 0
    TI__Guru**** 189039 points

    Hello Kanae, 

    Thank you for the query.

    Kanae said:
    but will you disclose the internal buses of other peripherals?

    Is there any specific peripheral that is of interest?

    Kanae said:
    Could you please describe them clearly in the TRM?

    Let me check and comeback.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Guru 10085 points

    Hi Sreenivasa,

    Thank you for your support.

    There is no specific peripheral.
    I would like to ask you to disclose documents that confirm the overall construction .
    Or I would like to know the reason why you do not disclose it.

    I am awaiting your reply.

    Best Regards,
    Kanae

  • 0 in reply to Kanae
    TI__Guru**** 189039 points

    Hello Kanae,

    Please refer the below chapter and other sections of the TRM (Chapter 1..4) for the available information.

    Chapter 11
    Data Movement Architecture

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Guru* 83745 points

    Hello Kanae-san

    Thank you for your query. We do not always publish bus topology information ,as this is mostly for advanced users and some times too much internal development that is not relevant for most development work. 
    Instead we publish key benchmarks in our Linux SDKs and MCU+ SDK and some times additionally have standalone application notes for device benchmarks and critical latency information. 

    I believe most of the other silicon vendors do the same and if they do have content  with more detail it is behind firewalls. 

    Our bus topologies are typically sized appropriately to manage the concurrency and arbitration requirements for standard use-cases, like the camera use-case you are talking about in the E2E, which Jianzhong has explained well. 

    At this time there are no plans to publish additional information in the TRM, we will keep this in our backlog as advance user information , but nothing that we currently have scheduled to work on. 

    If you have any other specific questions or concern on use-case , please feel free to post follow up question.

    Hope this helps

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Guru 10085 points

    Hi Mukul,

    Thank you for your reply.

    I understand your response that instead of information on bus topology,
    I will refer to the major benchmarks in the Linux SDK and MCU+ SDK,
    and that TI bus topologies are usually sized appropriately to manage
    the concurrency and arbitration required for standard use cases such as the camera use case. 

    I will try to explain the above to our customers and have them understand it.

    Any other specific questions or concerns regarding the use case will be posted.
    I appreciate your support.

    Best Regards,
    Kanae