This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: Support on issue about DSI clock lanes - Continue

Part Number: TDA4VM

Dear

Last time, I have a question here: Support on issue about DSI clock lanes

This issue is about the DSI clock lanes have only noise.

At the moment, after checking again the source code and hardware.

- Source code: there are no change in the default source code of TI.

- Hardware: the connection Test point <-> SOM CONN3 J5 is OK.

But the behavior still the same.

I can measure the DSI data lanes in the test points

But I cannot measure any valid signal of the DSI clock lanes

So I'd like to ask your support to consult us:

- Are there any chance or any other component can effect the DSI? Because it's strange when I can measure the Data Lanes but the Clock Lanes have issue

- Are there any source code that I should take care about that can cause the Clock Lane not work? Even in Linux side? As I understand the DSI is controlled by the R5.

- Are there any configuration that can cause this issue, like default config in header file, source file, device tree (kernel, uboot).We've modified the device tree by removing some parts but not sure it can effect the DSI or not.

Thank you

Best regards,

Loc.

  • Hi Loc,

    That's surprising. DSI cannot output data without clock and these lines are dedicated lines, so no other components from the SoC can affect clock lane output. Can you please check on the board if anything else is interfering with the board?

    Can you please run DSI standalone PDK based test case if possible? In this case, there is no possibility of any component interfering. 

    Regards,

    Brijesh

  • HI Brijesh,

    I'm now rebuild with the default source code.

    Can you please share me how to run the DSI test?

    Best regards,

    Loc.

  • Hi LoC, 

    Are you using vision apps ie flashing SD card? Then you need to enable DSI output in app_cfg_mcu2_0.h header file. Can you try disabling DP output and enabling DSI output in this file? You should then see some valid data + clock output on DSI.

    Regards,

    Brijesh

  • Hi Brijesh,

    Then you need to enable DSI output in app_cfg_mcu2_0.h header file. Can you try disabling DP output and enabling DSI output in this file

    Yes, that's exactly what I did. But I still cannot measure the clock

    I have a question about the clock. Can you share me what is the frequency of the DSI clock? Is it fixed like xxxMhz or it is adjustable? If it is adjustable, can you teach me how to do that, which are condition/parameters I should care, how can I calculate it? 

    Thank you.

    Best regards,

    Loc.

  • Hi Loc,

    In the default example, we are setting lane speed 850 to 970Mbps lane speed and this can be changed. In the API appDctrlSetDsiParamsCmd in the file app_dctrl.c, dsi_params params struct has an variable laneSpeedInKbps, you can change it to required output lane speed. 

    Regards,

    Brijesh

  • Hi Brijesh,

    Could you please help take a look in our measurement here:

    I try 2 measurement with below setup

    1. Measure in TI evaluation board (J721EVM)

    2. Measure in our custom HW

    I use the same software for both measurement with default configuration for DSI display in vision_apps.

    As you can see, the waveform is different between 2 HWs.

    So can you help me check with 2 question:

    1. With these waveforms, can you confirm which one is the correct form for the DSI continuous clock?

    2. Do you have any ideas why there is a difference here? Can this is the cause why my GMSL IC cannot detect the DSI clock because the waveform is not correct?

    Best regards,

    Loc.

  • Hi Loc,

    Well, the output on TDA4VM is tested with one of the SERDES combo, i would says EVM waveforms are from working condition. 

    Are there any board differences in terms of DSI output? Can you check if there is any board component differences on DSI path or any interference? 

    Also which SDK release are you using? Are you setting DSI output explicitly in control module register? This should have been taken care in the app_ini somewhere. 

    Regards,

    Brijesh 

  • Hi Brijesh,

    I'm using the SDK8.5 and using the default config for DSI. I just enable the DSI in the vision_apps config. That's all, and using the same software for measurement.

    I measure the DSI clock on the SOM CONN3 by connect copper wires here. Just like below image

    The only difference, in the board. I think is the DSI in TI Eval board is not connect to any thing while the DSI lines in our board is connect to GMSL IC.

    Do you think that could lead to this difference of the waveform?

    Best regards,

    Loc.

  • Hi Loc,

    Not an expert on board, so can't say from the board perspective. Has this board schematics been reviewed?

    Regards,

    Brijesh 

  • Hi Brijesh,

    In the default example, we are setting lane speed 850 to 970Mbps lane speed and this can be changed. In the API appDctrlSetDsiParamsCmd in the file app_dctrl.c, dsi_params params struct has an variable laneSpeedInKbps, you can change it to required output lane speed. 

    As I understand, this is about the video lane speed. Can you teach me how to calculate the Clock speed base on these value ( The value of DSI clock in Mhz)?

    Best regards,

    Loc.

  • Hi Loc,

    It is dependent on the output resolution, so width x height x bpp x fps is the total required speed and now just divide this number by number of lanes. 

    Regards,

    Brijesh