Part Number: TDA4VM
Dear Brijesh Jadav
Last time, I have a question here: Support on issue about DSI clock lanes
This issue is about the DSI clock lanes have only noise.
At the moment, after checking again the source code and hardware.
- Source code: there are no change in the default source code of TI.
- Hardware: the connection Test point <-> SOM CONN3 J5 is OK.
But the behavior still the same.
I can measure the DSI data lanes in the test points
But I cannot measure any valid signal of the DSI clock lanes
So I'd like to ask your support to consult us:
- Are there any chance or any other component can effect the DSI? Because it's strange when I can measure the Data Lanes but the Clock Lanes have issue
- Are there any source code that I should take care about that can cause the Clock Lane not work? Even in Linux side? As I understand the DSI is controlled by the R5.
- Are there any configuration that can cause this issue, like default config in header file, source file, device tree (kernel, uboot).We've modified the device tree by removing some parts but not sure it can effect the DSI or not.
Thank you
Best regards,
Loc.




