Dear Ti-Team,
we're currently working in the loading of the system firmware (M3 firmware loaded from MCU_R5FSS).
In the development our approach, the following questions emmerged:
Q1: Is MCU_NAVSS0_SEC_PROXY config (and hence by inheritance RING_ACC) determined by reset-defaults, or written by M3 ROM? (or a mix)
Q2: Is there a MCU_NAVSS0_PROXY and a MCU_NAVSS0_SEC_PROXY?
The system diagram does not show it, but for both MCU and MAIN domains there are mentions that, in both, there are proxies using a RING_ACC.
Q3 Regarding MCU_NAVSS0_SEC_PROXY, are there any features that make it "secure"?
Code does mention the optional secure header, but no further explanation is provided.
Q4: TRM B states (table 10-138) the MCU_NAVSS0_SEC_PROXY0 uses Ring accelerators 256 (inc) to 285 (inc). This equates to a total possible of 30 queues.
However, table 10-140 states the number of possible proxy threads is 90, with a default msg_size of 64.
Given it is not usable to have multiple
producers or consumers (due to credit arithmetic) for a single queue, the total number of threads should not have exceeded 30queues*2=60.
Is the 45thread-pairs to 30 queues really a design mismatch, or there are usage/other reasons for it?
Q5: Data WR flow:
- host FW writes to PROXY_MSG_DATA registers;
- Proxy copies it from aux buffers above;
- Proxy burst copies it to queue Ring interface
Data RD flow:
- host FW reads from PROXY_DATA:PROXY_MSG_DATA registers;
- Proxy burst copies it from queue Ring interface to aux buffer;
- Proxy copies it from aux buffers to PROXY_DATA:PROXY_MSG_DATA;
Is PROXY_DATA:PROXY_MSG_DATA a switch-mirror of buffer data, no actual copy occurs?
Q6: A CUR_CNT > MAX_CNT on the consumer/incoming will cause a producer or consumer ERROR flag, or both?
A CUR_CNT = 0 at the consumer followed by a write causes ERROR flag (on the producer/outgoing)?
Q7: Is MCU_NAVSS0_UDMASS_MSRAM0 & 1 the memory storage for the SEC_PROXY own RA queues?
(Main NAVSS has NAVSS0_MSRAM0 and UDMASS_MSRAM0 & 1... but MCU only shows UDMASS MSRAMs)
