Can DM8168 outputs analog RGB with separate H/V sync

PG1.1+ silicon can, yes.

On PG1.0 silicon you can use the DVO outputs and lock-step the DVO and DAC VENCs.

BR,

Steve

Hi Steve,

Thanks for your answer.

Could you please let me know how to do both in H/W and S/W in details ?

ex. Hardware circuit connect, Firmware programming procedure .

BR,

KS

Do you need this for PG1.0 or for newer silicon?

From a hardware perspective have a look at the attached as an example.

0550.THS8200 Graphics RD RevB.pdf

Software depends on which IO pins you want the signals to be present on, but you for PG1.1+ silicon you can use the following as a reference for setting the mux controls and IO function selections.

http://ap-fpdsp-swapps.dal.design.ti.com/index.php/Netra_DS_PG1.1_to_PG2.0

For PG1.0 silicon there is a procedure to lock-step 2 VENCs together so they are synchronized.

BR,

Steve

Hi Steve,

we are doing a feasibility study now, so we will use newer silicon.

I cannot access URL http://ap-fpdsp-swapps.dal.design.ti.com/index.php/Netra_DS_PG1.1_to_PG2.0,

could you please check it again.

Thanks a lot.

KS Lin

Hi Steve,

Thank you very much for your quickly answer.

KS

Hi Steve,

One more question, the solution you mentioned above is only for PG 2.0+ ? 

Thanks a lot

KS

What is the procedure for producing separate sync using the PG1.1 silicon? Does it require the same workaround as is described for the PG1.0?

Regards,

Ben

Ben,

PG1.0 does not have discrete DAC sync outputs so it is necessary to 'borrow' syncs from one of the DVO ports then synchronize the DAC VENC with the DVO VENC.

For PG1.1 and later there are discrete syncs available directly.

BR,

Steve

So then this procedure is valid for PG1.1?

HDVPSS: Horizontal and Vertical Sync Outputs for HD-DACs

• Details: HSYNC & VSYNC signals are brought out for HD-DACs
• Pin Mapping:

• HSYNC -- AR5/AT9/AR8
• VSYNC -- AL5/AP9/AL9

• Change pin names:

• Pins AR5 and AT9 - change VOUT[1]_HSYNC to DAC_VOUT[1]_HSYNC
• Pin AR8 - change VOUT[0]_AVID to DAC_HSYNC_VOUT[0]_AVID
• Pins AL5 and AP9 - change VOUT[1]_VSYNC to DAC_VOUT[1]_VSYNC
• Pin AL9 - change VOUT[0]_FLD to DAC_VSYNC_VOUT[0]_FLD

SPARE_CTRL0 Register (Base Address + 0x0724)

NOTE: When changing this register, read original value and write back same value in Reserved fields.

Eg. Steps required to use AR8 and AR9 as DAC_HSYNC/VSYNC signals:

• Set the pin muxing for AR8 and AL9 as follows:

• 0x48140894 = 0x00000001
• 0x48140898 = 0x00000001

• Select analog VENC sync out option as follows:

• 0x48140724 = 0x00000004

Ben,

I have just checked with the device owner and it appears that this was a PG2.0 change so the original posting last year is in fact not quite right.

The above is only valid for PG2.0 and later.

If you have a PG1.x device then you must use the DVO methodology to get discrete syncs.

The saving grace is that the PG1.x solution will also work on PG2.0 and later devices if you want to maintain a unified software.

Sorry for the confusion.

BR,

Steve

I'm still a little bit unsure of the function of the two bits - Is the following correct?

bit SPR_CTL0_2 affects pins AR8/AL9 only (depending on PINCTRL38/39 registers)

bit SPR_CTL0_1 affects pins AR5/AT9/AL5/AP9 only (depending on PINCTRL21/23/28/29)

Correct, SPR_CTL0_2 basically says 'replace VOUT[0]_AVID/FLD with DAC_HSYNC/VSYNC" wherever it might appear.

BR,

Steve

Is there a sync polarity control in software for the DAC_HSYNC/DAC_VSYNC bits?  I don't see anything in the display3 sysfs files.

Hi,

You could change the sync polarity using output sysfs attribute.

echo component/vga,rgb888/yuv422spuv,(0/1)/(0/1)/(0/1)/(0/1) > /sys/devices/platform/vpss/display3/output

Regards,

Brijesh Jadav

Thanks for the reply.  Some of those options don't appear on the wiki where I was looking:

http://processors.wiki.ti.com/index.php/DM816X_AM389X_VPSS_Video_Driver_User_Guide#VPSS_Driver

For display 3, output it says: 

Set the right VENC output

echo component/svideo/composite, rgb888/yuv444p/yuv422spuv > /sys/devices/platform/vpss/display3/output

the first part is the output mode, the second part is output data format.

Hi Andrew,

I checked in the code and it looks like you could set the polarity even for the DAC output. change the polarity, it should work.

We will change the documentation.

Regards,

Brijesh Jadav

I just tested this and it's doesn't seem to be working.  The sysfs arguments are accepted by the driver, but no change in polarity is observed on the outputs - they are always active high.  What I did was

echo "0" > /sys/devices/platform/vpss/display3/enabled
echo "component,rgb888,0/0/0/0" > /sys/devices/platform/vpss/display3/output
echo "1" > /sys/devices/platform/vpss/display3/enabled
./fbdemo

DAC_HSYNC and DAC_SYNC are active high.  I then repeated it 4 times and set each of the 4 polarity arguments to one in turn and probed the DAC_HSYNC and DAC_SYNC outputs with an oscilloscope.  In all cases the syncs kept to active high polarity and no change was observed on the monitor I had attached.

Hi Andrew, 

Could you please try below?

echo "0" > /sys/devices/platform/vpss/display3/enabled
echo "vga,rgb888,0/0/0/0" > /sys/devices/platform/vpss/display3/output
echo "1" > /sys/devices/platform/vpss/display3/enabled
./fbdemo

Regards,

Brijesh Jadav

This fails on line 2:

# echo "vga,rgb888,0/0/0/0" > /sys/devices/platform/vpss/display3/output
VPSS_DCTRL: invalid output value vga
sh: write error: Invalid argument

Hi Andrew,

Which silicon revision you are using? This is supported only on ES2.0, it is not supported on ES1.1 or ES1.0. Could you please check your silicon revision/

Also could you please check if vga is part of afmt_name in linux/drivers/video/ti81xx/vpss/sysfs.h? If it is not present, it is old release that you are using. Could you please update to new release?

If none of this work, could you please set the output component, rgb888, 1/1/1/1 and dump value of the offset 0x48108000 and share it with us?

Thanks,

Brijesh Jadav

Device is a DM8168BCYGA2 (aka ES2.0)

The release we are using is PSP 4.4.0.1 (vo vga entry for afmt_name), I am getting another engineer to build PSP 4.4.0.2 and update our filesystem and will report back to you.

With a kernel based on PSP 04.04.00.02 the vgas output mode works on display3 and DAC HSYNC and VSYNC perform as expected.  Thanks!

Good to hear it started working.