Other Parts Discussed in Thread: AM3356, SYSBIOS
Hi,
I was trying to use L2 cache lockdown feature to run critical code and data from locked down cache.
I have gone through cache lockdown code from Cortex A8 symbiose code.
When I am running my example code and measuring CPU cycles, instruction cycles and L2 read via PMU counter,
I can see L2 miss event is reduced to zero but not seeing any performance improvement in terms of execution time.
My CPU running at AM3356 @ 600MHz, DDR at 400Mhz.
Pre data and code lockdown:
Post lockdown:
I tried both method to load data before locking one by using PLE and second by using LDR instruction.
But result are same.
