AM623: Schematic Review

Hello Santosh

Thank you for the query.

The schematics review is supported through TI sales/support.

Are you working with any TI sales/support?

Regards,

Sreenivasa

Hello Sreenivasa,

Thanks for your prompt reply. Currently I’m not working with any Sales/support team. How do I proceed from here?

Thanks,

Santosh

Hello Santosh, 

Thank you.

We typically do not support reviews over E2E. I will try to provide any possible support.

Please send the schematics over private chat.

I will try to support a quick check to see there are no critical variations and provide you with guideline that could help you do a self-review.

Help me understand the work location.

Regards,

Sreenivasa

Hello Sreenivasa,

Thanks for your help. I really appreciate it. I will share the schematic over private chat. I remotely work from Bangalore, India for a company based in Halifax, NS, Canada

How do I get in touch with Sales/support to get the schematic fully reviewed as well?

Thanks

Santosh

Hello Santosh, 

Thank you.

Santosh Vema said:

Thanks for your help. I really appreciate it. I will share the schematic over private chat. I remotely work from Bangalore, India for a company based in Halifax, NS, Canada

How do I get in touch with Sales/support to get the schematic fully reviewed as well?

The request has to come from the company you represent or work to the TI contact they may be working.

Regards,

Sreenivasa

Thanks Sreenivasa, I can request for the company. Can you direct me on how I should go about doing it?

Hello Santosh, 

Thank you.

The company will have to work with the TI sales/support. The request is submitted by the TI  sales/support.

Regards,

Sreenivasa

Hello Santosh, 

Received the schematics,

I see that the pin connectivity requirements for MCU_I2C and WKUP I2C is not followed.

There are additional updates that may be required.

As i review, please refer below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337851/faq-am625-q1-am620-q1-custom-board-hardware-design---guidelines-for-reuse-of-sk-am62-lp-schematics

This is an updated schematics in works with a number of design notes and schematics review notes.

Please read through and make possible updates.

Within the schematics, in the initial pages we have links to the schematics review checklist and the hardware design guide that can be followed

Regards,

Sreenivasa

Hello Santosh, 

Can you confirm if the schematics is complete or in design?

Regards,

Sreenivasa

Hello Sreenivasa,

Thanks for the FAQ, I will go through them. The schematic is complete. The connections go to a 200 pin SODIM connector, which is on the base board where the processor module will be connected.

Thanks,

Santosh

Hello Santosh, 

Thank you.

I am not able to see the bootmode configuration resistors on the board and hence checking.

None of the bootmode pins are recommended to be left open.

Please follow the FAQ schematics to configure the bootmodes.

Regards,

Sreenivasa

Thanks Sreenivasa. I will go through the FAQs and update the schematic. The design notes are really useful. 

Who should I contact to work with TI sales/support?

Hello Santosh, 

Thank you for the note. There are number of recommendations that you could follow.

Regards,

Sreenivasa

Hello Santosh, 

I assume the company in canada has a procurement team, They might have reached out to the TI before and could potentially help.

I will review the schematics and provide some pointers during this week.

we typically have a 2..3 weeks time period to support the review. 

Regards,

Sreenivasa

Thanks, will check with the production team to see if they have reached out to TI before. 
Thank you please keep posted on your suggestions. Meanwhile I will go through the documents and update the schematic accordingly.

Hello Santosh, 

Thank you.

Additionally, please read through the pin connectivity recommendations of the data sheet.

Regards,

Sreenivasa

Hello Santosh, 

The comments are really awesome. I really appreciate it.

Thank you. 

Here are the changes I have made:

Page5:
Moved the GPIO from GPMC0 to VOUT0 and couple of GPIO I moved to OSPI0
Added pull ups on I2C1
Added pull downs on USB_RCALIB

Page6:
Added crystal on WKUP
Added pullups on MCU_I2C

Just wondering why do we need both pull up and pull down for bootmode?

This add flexibility.  Please read through the boot mode section of the TRM and add the required resistors.

Also, since I'm not using CSI and OLDI interfaces, can I remove ferrites and caps for VDDA_CORE_CSI, CDDA_1V8_CSIRX, and VDDA_1V8_OLDI and leave their respective voltage pins on processor unconnected?

OLDI supply is recommended to be connected. You can delete the ferrite and bulk caps for OLDI supplies.

I'm going through your comments and will make changes to the schematic and send you the updated one

Regards,

Sreenivasa

Thanks Sreenivasa, please keep me posted once you have made your comments. 
So if I remove ferrites and bulk caps on OLDI and CSI, should connect these VDDA_CORE_CSI, CDDA_1V8_CSIRX, and VDDA_1V8_OLDI voltages to VDD_CORE?

Hello Santosh

Thank you.

I do not understand your query.

The OLDI supply needs to be connected. Add decaps. 

To be safe, i would recommend connecting the CSI supplies also along with decaps.

If you are sure, you do not need to do boundary scan testing, you could follow the pin connectivity recommendations.

...

Regards,

Sreenivasa

Understood, thanks. 
I'm trying to find why a 0201 or smaller package caps are recommended for pins CAP_VDDSx? I couldn't find this information in the datasheet.

Hello Santosh

Thank you.

These are caps for the internal LDOs and needs to be placed as close to the terminals (pads) as possible.

It is 0201 or similar.

I am not sure about the SK you referred but i would suggest looking into the SK design that you are referring and use similar capacitor in terms of size and voltage rating.

Other notes on the capacitor placement are added in the  schematics referenced in the FAQ.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337851/faq-am625-q1-am620-q1-custom-board-hardware-design---guidelines-for-reuse-of-sk-am62-lp-schematics

Regards,

Sreenivasa 

I was referring to PROC124E2A reference design. Which uses 0201 package capacitors, but I couldn't find the reasoning behind this, so thought will check with you. Thanks for making it clear.

Hello Santosh

Thank you and understand. 

The below references could help.

[FAQ] AM625 / AM623 / AM625-Q1 / AM62A7 Custom board hardware design – information related to the processor evaluation modules or starter kits

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1321636/am625-power-supply-design-with-pmic-without-pmic-based-design

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332316/faq-am625-am625-am623-custom-board-hardware-design---guidelines-for-reuse-of-sk-am62b-p1-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337851/faq-am625-q1-am625-q1-am620-q1-custom-board-hardware-design---guidelines-for-reuse-of-sk-am62-lp-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1340905/faq-am62a7-am62a7-q1-am62a3-am62a3-q1---custom-board-hardware-design---guidelines-for-reuse-of-sk-am62a-lp-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1340906/faq-am62p---custom-board-hardware-design--am62p-am62p-q1---guidelines-for-reuse-of-sk-am62p-lp-schematics

Regards,

Sreenivasa 

Thanks Sreenivasa. Are you still reviewing my updated schematics and send me your comments?

Hello Santosh

Thank you for checking.

I have shared the schematics with all major marks and expect you to read the schematics notes - D-Nore, R-Note and make the updates.

I can do one quick check after you have made all the updates.

Regards,

Sreenivasa

Hello Sreenivasa,

I have sent you the updated schematic, please review it. I haven't added the testpoints that you recommended, but will do that at the end.

Hello Santosh

Thank you. Will review and provide feedback late this week.

For the VMON_VSYS 

Please connect VMAIN to monitor.

It is meant to be a power-fail indicator for the main input (higher) voltage rail that enters
the PCB. For example, 5, 12, or 24 volts.
The error associated with this monitor would require you to set the threshold significantly
lower than the nominal to avoid false trigger
Refer System Power Supply Monitor Design Guidelines section of the data sheet

Regards,

Sreenivasa

Hello Santosh, 

Here are a few updates. Also please make sure the suggestion in the PDF i attached over private chat is taken care.

LFOSC

The 32K crystal load is 9 pF

You need to use 18 pF load caps 

The 32K has limited use case 

Provision to ground Xi is recommended.

HFOSC

The crystal load is 10 pF

Considering the stray cap, you may have to use 12 pF load caps 

Please make the updates.

Please read through the D-Notes and R-Botes relevant to the design and make the required updates.

I have limited time available to review.

Regards,

Sreenivasa 

Hello Santosh, 

The recommendation was to follow the SK schematics and update the package to 0201 for the CAP_VDDSx 1 uF caps.

Not sure if you have reviewed the schematics that i shared with inputs and the schematics that has the design and review notes.

Please review and make the required updates.

Regards,

Sreenivasa

Hello Sreenivasa,

Thanks for your quick response. I will make changes to the load caps as recommended. 
I forgot to mention I haven't changed the capacitor package size on CAP_VDDSx, which I will do. 
I wanted to quickly get back to you with all the major changes.

Thanks 

Santosh

Hello Santosh, 

Thank you.

Please review the inputs provided in the 2 PDF schematics files and make the required updates.

Regards,

Sreenivasa

Hello Sreenivasa,

Thanks, I received only one PDF schematic from you which is on April 3rd. Did you send another PDF schematic with your comments in it?

Thanks

Santosh

Hello Santosh, 

Thank you.

I shared one PDF - the reviewed PDF with comments.

The Other PDF is in the FAQ with design notes D-Note and Review Note R-Note.

Regards,

Sreenivasa

Oh got it. I thought you shared another one. 
I want to connect RSTOUTn(PMIC_PGOOD) pin on PMIC directly to MCU_PORz without the AND gate, how do I go about doing that?

Hello Santosh, 

Thank you.

The MCU_PORx is 3.3V tolerant.

You could pullup the PMIC_PGOOD and connect to the MCU_PORz input.

Note that the MCU_PORz (LVCMOS) input has slew rate requirements - slew should be less than 1000 ns.

You will have to adjust the pullup based on measurement.

Regards,

Sreenivasa

Thanks Sreenivasa. I have sent you the final schematic, I really appreciate it if you can please review it.

Hello Santosh, 

Thank you.

Bootmode - Use 10K for all the resistors configured as pulldown 

SoC_WARM_RESETz, MCU_RESETz - slow ramp RC input is not allowed. ramp should be less than 1000ns 

If RC is required, a Schmitt trigger based debounce logic is required to be used. Refer SK schematics. DNI the C alternatively.

PORz_OUT - add a TP for testing.

VDDA_SYS_MON - verify the divider ratio (refer data sheet)

I will provide the review feedback by end of the week.

Regards,

Sreenivasa

Thanks for your comments Sreenivasa. I will wait for your review feedback. 

Here is my calculation for the voltage divider at Vmon_Vsys. Let me know if this makes sense.

Hello Santosh, 

Thank you.

The VMON_VSYS is used for early indication of the main supply. 

The values look ok based on quick check.

Regards,

Sreenivasa

Sounds good. Waiting for your review feedback, so that I can finalize the schematic.

Thanks

Santosh

Hello Santosh, 

Thank you. Will try to provide possible inputs early next week.

Regards,

Sreenivasa

Hello Santosh, 

I reviewed the schematics over the weekend and provided inputs for updates as well as optimization.

Recommended References for self-review and design of custom board

AM62X
www.ti.com/.../sprad05b.pdf
www.ti.com/.../sprad21c.pdf
www.ti.com/.../sprad06.pdf
e2e.ti.com/.../faq-am625-am623-am625sip-am625-q1-am620-q1-custom-board-hardware-design---faqs-related-to-processor-collaterals-functioning-peripherals-interface-and-starter-kit

AM625SIP
https://www.ti.com/lit/ds/symlink/am625sip.pdf

Regards,

Sreenivasa

Thank you Sreenivasa. I will go through the comments and make necessary changes.

Hello Santosh, 

Thank you for the note.

Regards,

Sreenivasa

Hello Sreenivasa,

Just checking to see is a schmitt trigger buffer really necessary on MCU_PORz, as I have space constraints on my board.

Thanks

Santosh

Hello Santosh, 

Thank you.

Using Schmitt is recommended to minimize internal reset glitch..

In case you are considering to use the Open drain output of the PMIC to reset the SOC the concern is the slow rise time.

Provide a strong pull to minimize the rise time of the SOC  MCU_PORz input.

I understand you do not have an use case for frequent power cycling of the End Equipment.

Regards,

Sreenivasa

Thanks Sreenivasa for your quick response.

Hello Santosh, 

Thank you.

Regards,

Sreenivasa