Hi Experts,
Please tell me about the relationship between CLKIN and McBSP output clock(CLKX) in TMS320VC5509A.
CPU CLOCK is generated by multiplying CLKIN by 4 using the internal PLL.
McBSP's output clock (CLKX) is generated by McBSP's Sample Rate Generator, which divides the CPU CLOCK.
Is it possible to set the CLKX edge timing and CLKIN edge timing to the same position every time even after resetting?
When using 5509A, there is a timing that matches the CPU CLOCK multiplier.
But using 5409, the timing of CLKIN and BCLKX(Equivalent to CLKX of 5509A) is always constant. (Independent of multiplier)
Best regards,