We are using TPS6521903RHB PMIC for the processor AM6254ATCGGAALW and there are some power nets which are mentioned more than once in the power up sequence. please help us to understand more about it.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
We are using TPS6521903RHB PMIC for the processor AM6254ATCGGAALW and there are some power nets which are mentioned more than once in the power up sequence. please help us to understand more about it.
Hi,
Thanks for reaching out. The notes at the bottom of that table explains the supply consolidations that are allowed. For example, when VDD_CORE runs at 0.85V, the same PMIC rail is used to supply both CORE domains (VDD_CORE and VDDR_CORE) so they ramp together. Some of the other signals in the "B" and "C" waveforms are dual voltage IO (3.3V/1.8V) so their sequence requirements will depend on the voltage used.
Let us know about your specific question and we will be happy to answer.
Thanks,
Brenda