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TDA4VH-Q1: Micron EMMC adaption

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

start log.txt

Hello:

  At present, we use Micron's MTFC128GBCAQTC-AAT chip for TDA4VH chip and SDK version 0900. During HS400 startup, EMMC speed switching fails, and the error returns -84. If we switch to DDR52 startup, it is normal, and the log is shown as follows: The Micron MTFC32GBCAQTC-AAT chip can be started normally, we have correctly configured the partition information, non-memory space issues. Before, we encountered the problem of returning -110 when adapting other EMMC. The actual test showed that the phase of CLK corresponding to CMD in the speed switching function of TDA4VH platform would change, resulting in the failure of correct sampling of CMD. However, the error returned this time is different, please provide support from TI team. How do we adapt this EMMC chip?

  • HI jingle

    How many of the board having this issue ? is it all i dont think we need to do any driver changes specific to the emmc device.

    What the speed mode you are using in U-BOOT ?

    Regards
    Diwakar

  • At present, 30 PCBS have been produced, and 5 of them have the above problems.
    The system board two TDA4VH chips, Layout is completely reusable, using 32GB EMMC there is no problem. This is because the EMMC chip master sampling should be able to correctly collect the offset cmd command.

  • Hi Diwakar 

    This problem occurs in the EMMC switch speed driver, which sometimes returns -110, because emmc does not correctly recognize the cmd6 command sent by TDA4, and sometimes returns -84.

  • The Uboot uses DDR52

  • HI jingle

    Can we set the HS400 speed mode in the UBOOT as well so that we will be sure that no issue with linux driver.

    Have you tried HS200 speed mode in linux?

    Help share the dtb which you used during testing of HS400.

    Regards
    Diwakar

  • Hi Diwakar 

    We tested with HS200 and HS400 in uboot, and the boot process worked fine. Everything worked fine until EMMC failed to switch from HS400 to HS200, and then prompted a read/write error.

    Why switch from HS400 to HS200 and then to HS400 in TI? How do we turn off switching from HS400 to HS200 in Kernal?

  • HI jingle

    We tested with HS200 and HS400 in uboot, and the boot process worked fine. Everything worked fine until EMMC failed to switch from HS400 to HS200, and then prompted a read/write error.

    This statement is bit confusing for me are you saying the HS400 is working fine in UBOOT ?

    Why switch from HS400 to HS200 and then to HS400 in TI? How do we turn off switching from HS400 to HS200 in Kernal?

    This is nothing specific to TI , this is as per JEDEC spec in order to perform the tuning operation for HS400 speed mode we need to switch to HS200.

    Regards
    Diwakar 

  • Hi Diwakar 

    HS200 and HS400 work fine in Uboot。HS400 then starts, and in kernal there will be HS400 to HS200, where CMD will return -110。

    Please see the attached picture above, where the phase of cmd and clk has changed.

  • HI jingle

    Can you share me below command output in UBOOT in HS400 case 
    • mmc dev 0
    • mmc info 

    Switching between the speed will also be  happening in uboot as well.

    Regards
    Diwakar

     
  • HI jingle

    Can you help me with the below details:

    • UBOOT and LINUX dtb 
    • Can you add enable more logs in below modules and share the logs
        sdhci
        mmc_block
        cqhci
        sdhci_am654
        mmc_core

    Regards
    Diwakar

  • Update some information:

    We tried the following:

    uboot

    Linux

    System status

    ddr52 or hs200 or hs400

    ddr52

    hs200

    hs400

    X

     

    1There is no problem with uboot all modes.

    2When I keep the HS400 settings on Linux, delete other property, the compiled image will apply DDR52.

    Here is the linux dts:

    mmc@4f80000 {

                         compatible = "ti,j721e-sdhci-8bit";

                         reg = <0x0 0x4f80000 0x0 0x1000 0x0 0x4f88000 0x0 0x400>;

                         interrupts = <0x0 0x3 0x4>;

                         power-domains = <0x10 0x8c 0x1>;

                         clocks = <0xf 0x8c 0x1 0xf 0x8c 0x2>;

                         clock-names = "clk_ahb", "clk_xin";

                         assigned-clocks = <0xf 0x8c 0x2>;

                         assigned-clock-parents = <0xf 0x8c 0x3>;

                         bus-width = <0x8>;

                         ti,otap-del-sel-legacy = <0x0>;

                         ti,otap-del-sel-mmc-hs = <0x0>;

                         ti,otap-del-sel-hs400 = <0x8>;

                         ti,itap-del-sel-legacy = <0x10>;

                         ti,itap-del-sel-mmc-hs = <0xa>;

                         ti,strobe-sel = <0x77>;

                         ti,clkbuf-sel = <0x7>;

                         ti,trm-icp = <0x8>;

                         mmc-hs400-1_8v;

                         dma-coherent;

                         status = "okay";

                         non-removable;

                         ti,driver-strength-ohm = <0x32>;

                         disable-wp;

                         phandle = <0xf0>;

                  };

    3When I set it as follows, the system will not boot, you can refer to the log file

    Linux dts:

    Set HS400 mode

     

     

    Uboot dts:

    Set DDR52 mode

     

    1258.log.txt

  • Hi xuefei

    I could also see the n number of recovery in the logs shared by you 

    trying mode MMC DDR52 (52MHz) width 8 (at 52 MHz)
    selecting mode MMC DDR52 (52MHz) (freq : 52 MHz)
    [ 1.912375] mmc0: running CQE recovery
    [ 1.912881] mmc0: CQE recovery done
    [ 1.930659] mmc0: CQE recovery start
    [ 1.930663] mmc0: running CQE recovery
    [ 1.931071] mmc0: CQE recovery done
    [ 1.975064] mmc0: CQE recovery start
    [ 1.975069] mmc0: running CQE recovery
    [ 1.980779] mmc0: CQE recovery done
    [ 1.980918] mmc0: failed to start CQE transfer for tag 25, error -16
    [ 1.980940] mmc0: CQE recovery start
    [ 1.980942] mmc0: running CQE recovery
    [ 2.116900] mmc0: CQE recovery start
    [ 2.116906] mmc0: running CQE recovery
    [ 2.117118] mmc0: req done (CMD12): -110: 00000000 00000000 00000000 00000000
    [ 2.117227] mmc0: 0 bytes transferred: -84
    [ 2.117311] mmc0: CQE recovery done
    [ 2.120900] mmc0: req failed (CMD13): -84, retrying...
    [ 2.120994] mmc0: req failed (CMD13): -84, retrying...
    [ 2.121136] mmc0: req failed (CMD6): -84, retrying...
    [ 2.121232] mmc0: req failed (CMD6): -110, retrying...
    [ 2.121327] mmc0: req failed (CMD6): -84, retrying...
    [ 2.121413] mmc0: req done (CMD6): -110: 00000000 00000000 00000000 00000000
    [ 2.121427] mmc0: mmc_hs400_to_hs200 failed, error -110
    [ 2.121437] mmc0: failed to start CQE transfer for tag 18, error -110
    [ 2.121526] mmc0: starting CQE transfer for tag 19 blkaddr 4149248
    [ 2.125498] mmc0: CQE recovery done
    [ 2.125624] mmc0: CQE recovery start
    [ 2.125626] mmc0: running CQE recovery
    [ 2.125707] mmc0: sdhci: CQE off, IRQ mask 0xff0003, IRQ status 0x0
    [ 2.125886] mmc0: 0 bytes transferred: -84
    [ 2.125893] I/O error, dev mmcblk0, sector 1359016 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 2
    [ 2.125921] mmc0: CQE recovery done

    can you check if your IO voltage is stable in HS400 case?

    Regards
    Diwakar

  • can you check if your IO voltage is stable in HS400 case?

    yes, even if the system cannot enter the rootfs, the IO voltage is stable at 1.8V.

    I measured here.

  • How about here 

    Regards
    Diwakar

  • the same, all 1.8v

  • HI xuefei

    Have you tried changing the otap values ?

    can you try modifying the value one by one and see if makes any improvement.

    Also it will be good if we can get the waveform for HS400 in the UBOOT as well.

    Regards
    Diwakar