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Original question:

PHYTC-3P-KIT-AM64: MCSPI communication TX only mode: Using both data lines for TX to send different data

AM625: If SPI is set to SLAVE mode, is it able to update transmission data to Shift Register via DMA controller?

Daniel Cheng1
Mastermind 7165 points
Part Number: AM625

Hi Expert,

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1268780/phytc-3p-kit-am64-mcspi-communication-tx-only-mode-using-both-data-lines-for-tx-to-send-different-data

I see the article. It used 2 SPI port to make the MCU have 2 Shift Registers and able to send different data in the same time.
But I see one of the SPI is set to SLAVE mode to make the transmission Clock Phase Synchronize each other.
I have a question. If SPI is set to SLAVE mode, is it able to update transmission data to Shift Register via DMA controller?
If it is able, that is the solution we want, else I think we need to update Shift Register manually. That means the CPU load will rise up a lot when sending Data.

And additional information of application, application needs to send data by Maximum clock Rate(50Mbits) and continually. So we need to send data via DMA.

Thanks

Daniel

  • 0
    TI__Mastermind 45906 points

    Hi Daniel,

    Thanks for your question.

    Daniel Cheng1 said:
    If SPI is set to SLAVE mode, is it able to update transmission data to Shift Register via DMA controller?

    So, as far as we are intiating a transfer more specifically MCSPI_Transfer() API for Slave as well, then there should be no problem having the data sent over wether it be with or without DMA.

    Yes the Clock Frequency of 50 MHz is feasible and can be used.

    Regards,

    Vaibhav