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DRA829J: MCSPI: Master Receive-Only Mode, issue with receiving 1 byte

Dmitry Tuykov
Expert 1221 points
Part Number: DRA829J

Dear TI-Team,

I'm trying to optimize our MCSPI driver and faced and issue that I cannot receive 1 word of data (1 byte) in the following configuration:

  • Master, single channel mode
  • TRM = 1 (receive-only)
  • FFER = 1
  • FFEW = 0
  • Turbo = 1
  • MCSPI_XFERLEVEL:WCNT = num_of_bytes (1 in current case)

For any other amount of data it work perfectly fine. One byte is receive sometimes but randomly and quite rare.

I found the following thread where probably the similar issue is described: AM335x McSPI Receive Only mode needs a dummy transmit - Processors forum - Processors - TI E2E support forums

But I do not use DMA and have no ideas how to make it running for one byte.

What I tried to change Turbo from 1 to 0 in case of receiving 1 byte, sometimes it works, sometimes make channel completely locked (TXS = 0) and it cannot be used again.

Do you have any recommendations of using receive-only mode without DMA for 1 word (byte) of data?

Thanks,
Dmitry

  • 0
    TI__Guru 50426 points

    Hello,

    Few question before answering here,

    Which McSPI driver are you optimising here ? PDK driver or MCAL driver ?

    and also let me know which SDK version you are on?

    Regards

    Tarun Mukesh

  • 0 in reply to Tarun Mukesh Puvvada
    Expert 1221 points

    Hi Tarun,

    it is our custom driver developed based on the TI documentation.

    All in all I'm trying to understand how to receive 1 byte in Receive-Only + Turbo Mode.

    If combination above is not possible for any reason (please confirm), I would like to ask which combination of transfer mode + Turbo is suitable for 1 byte reception. Currently I was successful in using Transmit-Receive + Turbo, but wonder why Receive-Only + Turbo does not work for 1 byte reception. 

    Regards,
    Dmitry

  • 0 in reply to Dmitry Tuykov
    TI__Guru 50426 points

    Hello,

    Turbo mode is time saving when a transfer exceeds two words.

    In turbo mode, Rule 1 and Rule 2 apply, but Rule 3 does not . An enabled channel can be scheduled if its receive register is full (the /1/2/3[0]RXS bit) when the shift-register is assigned until the shift register is full.

    The /1/2/3 register cannot be overwritten in turbo mode. Consequently, the [3] RX0_OVERFLOW bit is never set
    in this mode.

    • Rule 1: Only enabled channels (the /1/2/3[0] EN bit) can be scheduled for transmission and/or reception.
    • Rule 2: If its /1/2/3 transmitter register is not empty (the /1/2/3[1] TXS bit), an enabled channel can be
    scheduled when the shift register is assigned. If the /1/2/3 register is empty when the shift register is
    assigned, the TXx_UNDERFLOW event is activated, and the next enabled channel with new data to transmit
    is scheduled (see also transmit-only mode).
    • Rule 3: An enabled channel can be scheduled if its receive register is not full (the /1/2/3[0] RXS bit) when the
    shift register is assigned (see also receive-only mode). Therefore, the /1/2/3 register cannot be overwritten.
    The [3] RX0_OVERFLOW bit is never set to this mode.

    Regards

    Tarun Mukesh