TDA4VM: how to add MCU_RGMII1 eth1 interface?

Hi,

xu hao said:

   we connect MCU_CPSW2G_RGMII to DP83867 in hardware and want to add a new eth inetrafce for it.

  how to config dtsi and modify code, please help.

By default MCU CPSW2G is enabled in HLOS like Linux and is configured with RGMII as TI EVM also has the same connection.
Please refer to "k3-j721e-common-proc-board.dts", for more details.


Best Regards,
Sudheer

Dear TI,

  we change MCU_RGMIi1_INT of DP83867 in hardware, how to config this in dts and code?
  please help.

Hi,

xu hao said:

we change MCU_RGMIi1_INT of DP83867 in hardware, how to config this in dts and code?

Do you mean INT signal from PHY as shown in below? CPSW don't have INT signal and is not supported.

MDIO state machine in Linux takes care of PHY Link Status checking? Interrupt mode of PHY is not supported from CPSW point of view.

If you need support related to PHY, it will be different forum. Please raise Query with PHY Name title.

Best Regards,
Sudheer

Dear TI,

  we get below error, how to analysis this kind of problem?

  [uart log]

  Net: Could not get PHY for ethernet@46000000port@1: addr 0
  am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed

Hi, 

xu hao said:

Net: Could not get PHY for ethernet@46000000port@1: addr 0
  am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed

Above device tree configuration is reference from TI SDK. 

On TI EVM phy connected to MCU CPSW2G with address 0 so, we used phy@0 and reg value of 0.

You need to modify phy address as per your board schematic. 

Best Regards, 

Sudheer

Dear TI,

  after check with hardware, we change DP83867 PWDN/MCU_RGMII1_INT from WKUP_GPIO0_55 to WKUP_GPIO0_10, how to config this in dts and code?

Hi,

xu hao said:

  after check with hardware, we change DP83867 PWDN/MCU_RGMII1_INT from WKUP_GPIO0_55 to WKUP_GPIO0_10, how to config this in dts and code?

Can you please share your dts file which using WKUP_GPIO0_55  as reset signal for PHY.
May be you can change the number 55 to 10 at the MDIO "reset-gpios" signal.

Best Regards,
Sudheer

Dear TI, 

  from EVM hardware circuit we see the EVM use WKUP_GPIO0_55 as MCU_CPSW/DP83867 PWDN, but i cannot find it in dts and code.
  please help

Dear TI,

  i find cpsw_port1 was mac-only in dts, how to modify code and dts to make it can connet internet?

  please help.

  [dts] k3-j721e-mcu-wakeup.dtsi
  mcu_cpsw: ethernet@46000000 {
      ethernet-ports {
          cpsw_port1: port@1 {
              ti,mac-only;
              label = "port1";
          };
  };

Hi,

xu hao said:

  i find cpsw_port1 was mac-only in dts, how to modify code and dts to make it can connet internet?

  please help.

  [dts] k3-j721e-mcu-wakeup.dtsi
  mcu_cpsw: ethernet@46000000 {
      ethernet-ports {
          cpsw_port1: port@1 {
              ti,mac-only;
              label = "port1";
          };
  };

  

Yes, CPSW2G Port is MAC Port.

You can connect CPSW2G to DHCP network and you will get IP for the interface. You need to connect CPSW2G to your internet network.

No need of any configuration from device tree to connect CPSW2G to internet.

Best Regards,
Sudheer

Dear TI,

  i get eth0 for am65-cpsw-nuss, but cannot connect internet

  our SDK version is 08.06.00.11, please help check the log.

  thanks!

ecar.txt

Hi,

xu hao said:

i get eth0 for am65-cpsw-nuss, but cannot connect internet

what do you mean by internet connect? Is it CPSW2G and EthFw communication?

If so, you need to connect CPSW2G Port to CPSW9G switch port.

Can you please share EthFw Debug log as well?

I can see you are trying ping with 192.168.1.200 and assigning IP of 192.168.1.220 to eth0.

Can you also confirm IP of eth0 just before running ping.

Can you please similar log after making above along with EthFw log.

Best Regards,
Sudheer

Dear TI,

  1 i want to ping from TDA4VM company board to my windows PC, the board ip is 192.168.1.220, my pc ip is 192.168.1.200, i have checked both side.

  hardware design we connect MCU_RGMII1 to DP83867, then connect to RJ45，not through CPSW9G router

  please show me the cmd to catch ethfw log and whether need to turn on some log level

2 after compare with TI TDA4VM EVB mcu_cpsw which ping is OK, i found below logs are missing in our company board, which can cause this?

  please help

  [missing log]

  [ 133.412179] am65-cpsw-nuss 46000000.ethernet: down msc_sl f0000018 tmo 0
  [ 133.421126] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48

  EVB.txt

Hi,

xu hao said:

  1 i want to ping from TDA4VM company board to my windows PC, the board ip is 192.168.1.220, my pc ip is 192.168.1.200, i have checked both side.

Okay. After seeing the IP 192.168.1.200 I thought CPSW9G is connected because it was static IP of EthFw.

If CPSW2G is directly connected to PC, No need to check EthFw side logs.

xu hao said:

2 after compare with TI TDA4VM EVB mcu_cpsw which ping is OK, i found below logs are missing in our company board, which can cause this?

  please help

  [missing log]

  [ 133.412179] am65-cpsw-nuss 46000000.ethernet: down msc_sl f0000018 tmo 0
  [ 133.421126] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48

It may not be because of this. As I could see Link Up message from your logs.

am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx

Can you please check CPSW statistics while running ping from eth0 (CPSW2G interface).
# ethtool -S eth0

Check Tx packet count of Port-1 and Rx packet count of Host Port. Please share the logs with us by capturing statistics at two or three instance while running ping command.

Best Regards,
Sudheer

Dear TI,

  i fount the tx number of board side is increasing, the rx number of pc side remain the same, it seems pc have not receive the packet from board.

  but the rx number of pc side is increasing.

  log is attached, please check

 [log]

 tx_good_frames: 61
 tx_good_frames: 82
 tx_good_frames: 93
 tx_good_frames: 108
 tx_good_frames: 125

7853.ethtool.txt

Hi,

I could see Rx align error counters are increasing at Board side.

rx_align_code_errors: 697
rx_align_code_errors: 979
rx_align_code_errors: 1157
rx_align_code_errors: 1354


Can you please check Rx delay at PHY side is enabled or not? If not enabled can you check by enabling the Tx delay at PHY side?

Can you check once if delay is handled from PCB traces then PHY side delay should be disabled.

Also, please capture the packets at PC side by opening Wireshark and check packet are received properly from PCB and PC sending ping response or not?

Best Regards,
Sudheer

Dear TI,

  1 in TI SDK ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>, test not work

  current i set ti,rx-internal-delay = <0x0>;ti,tx-internal-delay = <0x4>; according to log

  [uart log]

  [ 62.691200] TI DP83867 46000f00.mdio:00: PHY has delays via pin strapping, but phy-mode = 'rgmii'
  [ 62.691200] Should be 'rgmii-id' to use internal delays txskew:4 rxskew:0

  Wireshark is attached, please check.

  2 how to set rx-internal-delay and tx-internal-delay in dts, please help.

TDA40510.zip

Hi,

xu hao said:

TDA40510.zip

It seems like Tx from Board is working fine, so only you are observing the packets sent from Board  (ARP request) in Wireshark.
But, Board is not receiving any packets sent from PC so ARP is not resolved at Board side.

Rx delay can't be enabled on MAC. It should be from PHY side.

Please refer to FAQ [How to handle RGMII delays]

Also, refer to below.
https://patchwork.kernel.org/project/linux-amlogic/patch/20161125131201.19994-2-martin.blumenstingl@googlemail.com/

Best Regards,
Sudheer

Dear TI,

  should we check the tcpdump of the board side?

  we use the same hardware design as TDA4VM EVB, it should not have rx delay problem.

Hi,

xu hao said:

  should we check the tcpdump of the board side?

  we use the same hardware design as TDA4VM EVB, it should not have rx delay problem.

You can run tcpdump on Linux A72 terminal with CPSW2G interface.
As I have pointed above CPSW Rx has alignment error. It will be due to RGMII Delay Issue.

Can you check by configuring mode as "rgmii" instead of rgmii-rxid and remove delay details from mdio node . So that delay at PHY side will be disabled. 

Best Regards,
Sudheer

Dear TI,

  after change rx-internal-delay to 2_75_NS and 3_00_NS the board can receive packet, but the packet loss rate is up to 80%-90%.

  how to solve this problem? please help.

  packetlose.zip